_A(S3C24X0_INTCTL_PA_BASE),
_S(S3C24X0_INTCTL_SIZE),
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
_A(S3C24X0_TIMER_BASE),
_A(S3C24X0_TIMER_PA_BASE),
_S(S3C24X0_TIMER_SIZE),
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
_A(S3C24X0_UART0_BASE),
_A(S3C24X0_UART0_PA_BASE),
_S(S3C24X0_UART_PA_BASE(3) - S3C24X0_UART0_PA_BASE),
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
_A(S3C24X0_WDT_BASE),
_A(S3C24X0_WDT_PA_BASE),
_S(S3C24X0_WDT_SIZE),
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
0,
0,
0,
0,
int prio;
int unit;
struct {
int type;
u_long start;
u_long count;
} res[2];
} s3c24x0_children[] = {
{ "rtc", 0, -1, {
{ SYS_RES_IOPORT, S3C24X0_RTC_PA_BASE, S3C24X0_RTC_SIZE },
{ 0 },
} },
{ "timer", 0, -1, { { 0 }, } },
{ "uart", 1, 0, {
{ SYS_RES_IRQ, S3C24X0_INT_UART0, 1 },
{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(0),
S3C24X0_UART_BASE(1) - S3C24X0_UART_BASE(0) },
} },
{ "uart", 1, 1, {
{ SYS_RES_IRQ, S3C24X0_INT_UART1, 1 },
{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(1),
S3C24X0_UART_BASE(2) - S3C24X0_UART_BASE(1) },
} },
{ "uart", 1, 2, {
{ SYS_RES_IRQ, S3C24X0_INT_UART2, 1 },
{ SYS_RES_IOPORT, S3C24X0_UART_PA_BASE(2),
S3C24X0_UART_BASE(3) - S3C24X0_UART_BASE(2) },
} },
{ "ohci", 0, -1, {
{ SYS_RES_IRQ, S3C24X0_INT_USBH, 0 },
{ SYS_RES_IOPORT, S3C24X0_USBHC_PA_BASE, S3C24X0_USBHC_SIZE },
