static void s3c6410_i2c_init(void)
{
struct clk *clk;
unsigned long tmp;
clk = clk_get(NULL, "i2c");
clk_enable(clk);
// 选择引脚功能：GPE15:IICSDA, GPE14:IICSCL
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
/* bit[7] = 1, 使能ACK
* bit[6] = 0, IICCLK = PCLK/16
* bit[5] = 1, 使能中断
* bit[3:0] = 0xf, Tx clock = IICCLK/16
* PCLK = 50MHz, IICCLK = 3.125MHz, Tx Clock = 0.195MHz
*/
tmp = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
tmp = S3C2410_IICCON_ACKEN | S3C2410_IICCON_TXDIV_16 | S3C2410_IICCON_IRQEN | S3C2410_IICCON_SCALEMASK;
writel(tmp, s3c6410_i2c_xfer_data.regs + S3C2410_IICCON);
//s3c6410_i2c_regs->iiccon = (1<<7) | (0<<6) | (1<<5) | (0xf); // 0xaf
tmp = readb(s3c6410_i2c_xfer_data.regs + S3C2410_IICADD);
tmp = 0x10; /* slave_addr */
writeb(tmp, s3c6410_i2c_xfer_data.regs + S3C2410_IICADD);
//s3c6410_i2c_regs->iicadd = 0x10; // S3C24xx slave address = [7:1]
tmp = readl(s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);
tmp = 0x10;
writel(tmp, s3c6410_i2c_xfer_data.regs + S3C2410_IICSTAT);
//s3c6410_i2c_regs->iicstat = 0x10; // I2C串行输出使能(Rx/Tx)
}
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
}
static int s3c_irda_startup(struct s3c_irda *si)
{
int ret;
DBG("%s\r\n", __FUNCTION__);
/* Ensure that the ports for this device are setup correctly */
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
#elif defined(CONFIG_CPU_S5PC100)
s3c_gpio_setpull(S5PC1XX_GPA1(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S5PC1XX_GPA1(3), S3C_GPIO_PULL_UP);
#endif
ret = s3c_irda_sir_init(si);
if(ret) {
printk("Irda Startup failed\r\n");
return ret;
}
ret = s3c_irda_set_speed(si, si->speed = 9600);
if(ret)
s3c_irda_sir_stop(si);
return ret;
}
static int hmt_bl_init(struct device *dev)
{
int ret;
ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
if (!ret)
ret = gpio_direction_output(S3C64XX_GPB(4), 0);
return ret;
}
static void s3c_irda_gpio_conf(void)
{
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_UART_RXD3);
s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_UART_TXD3);
#elif defined(CONFIG_CPU_S5PC100)
s3c_gpio_cfgpin(S5PC1XX_GPA1(2), S5PC1XX_GPA1_2_UART_3_RXD);
s3c_gpio_cfgpin(S5PC1XX_GPA1(3), S5PC1XX_GPA1_3_UART_3_TXD);
#endif
}
static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
{
pr_debug("%s: setting power %d\n", __func__, power);
if (power) {
gpio_set_value(S3C64XX_GPB(0), 1);
msleep(1);
s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
} else {
gpio_direction_output(S3C64XX_GPF(14), 0);
gpio_set_value(S3C64XX_GPB(0), 0);
}
}
static void __init crag6410_machine_init(void)
{
/* Open drain IRQs need pullups */
s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
gpio_request(S3C64XX_GPB(0), "LCD power");
gpio_direction_output(S3C64XX_GPB(0), 0);
gpio_request(S3C64XX_GPF(14), "LCD PWM");
gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
gpio_request(S3C64XX_GPB(1), "SD power");
gpio_direction_output(S3C64XX_GPB(1), 0);
gpio_request(S3C64XX_GPF(10), "nRESETSEL");
gpio_direction_output(S3C64XX_GPF(10), 1);
s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
s3c_i2c0_set_platdata(&i2c0_pdata);
s3c_i2c1_set_platdata(&i2c1_pdata);
s3c_fb_set_platdata(&crag6410_lcd_pdata);
dwc2_hsotg_set_platdata(&crag6410_hsotg_pdata);
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
samsung_keypad_set_platdata(&crag6410_keypad_data);
s3c64xx_spi0_set_platdata(NULL, 0, 2);
pwm_add_table(crag6410_pwm_lookup, ARRAY_SIZE(crag6410_pwm_lookup));
platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
gpio_led_register_device(-1, &gpio_leds_pdata);
regulator_has_full_constraints();
s3c64xx_pm_init();
}
void s3c_setup_uart_cfg_gpio(unsigned char hwport, struct uart_port* port)
{
switch (hwport)
{
case 0:
s3c_gpio_cfgpin(S3C64XX_GPA(0),S3C64XX_GPA0_UART_RXD0);
s3c_gpio_setpull(S3C64XX_GPA(0), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPA(1),S3C64XX_GPA1_UART_TXD0);
s3c_gpio_setpull(S3C64XX_GPA(1), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPA(2),S3C_GPIO_INPUT);
s3c_gpio_setpull(S3C64XX_GPA(2), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPA(3),S3C_GPIO_OUTPUT);
s3c_gpio_setpull(S3C64XX_GPA(3), S3C_GPIO_PULL_DOWN);
wr_regb(port, S3C_UMSTAT, 0);
break;
case 1:
s3c_gpio_cfgpin(S3C64XX_GPA(4),S3C64XX_GPA4_UART_RXD1);
s3c_gpio_setpull(S3C64XX_GPA(4), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPA(5),S3C64XX_GPA5_UART_TXD1);
s3c_gpio_setpull(S3C64XX_GPA(5), S3C_GPIO_PULL_DOWN);
//s3c_gpio_cfgpin(S3C64XX_GPA(6),S3C64XX_GPA6_UART_nCTS1);
s3c_gpio_setpull(S3C64XX_GPA(6), S3C_GPIO_PULL_DOWN);
//s3c_gpio_cfgpin(S3C64XX_GPA(7),S3C64XX_GPA7_UART_nRTS1);
s3c_gpio_setpull(S3C64XX_GPA(7), S3C_GPIO_PULL_DOWN);
wr_regb(port, S3C_UMSTAT, 0);
break;
case 2:
s3c_gpio_cfgpin(S3C64XX_GPB(0),S3C64XX_GPB0_UART_RXD2);
s3c_gpio_setpull(S3C64XX_GPB(0), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPB(1),S3C64XX_GPB1_UART_TXD2);
s3c_gpio_setpull(S3C64XX_GPB(1), S3C_GPIO_PULL_DOWN);
break;
case 3:
printk("UART 3 is used as I2C bus in M8\n");
break;
default:
printk("Unknown UART port ID\n");
break;
}
}
static int hmt_bl_notify(struct device *dev, int brightness)
{
/*
* translate from CIELUV/CIELAB L*->brightness, E.G. from
* perceived luminance to light output. Assumes range 0..25600
*/
if (brightness < 0x800) {
/* Y = Yn * L / 903.3 */
brightness = (100*256 * brightness + 231245/2) / 231245;
} else {
/* Y = Yn * ((L + 16) / 116 )^3 */
int t = (brightness*4 + 16*1024 + 58)/116;
brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
}
gpio_set_value(S3C64XX_GPB(4), brightness);
return brightness;
}
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
writel(reg | MEM_SYS_CFG_INDEP_CF |
MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}
void s3c64xx_ide_setup_gpio(void)
{
u32 reg;
reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
/* Independent CF interface, CF chip select configuration */
writel(reg | MEM_SYS_CFG_INDEP_CF |
MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
/* Set XhiDATA[15:0] pins as CF Data[15:0] */
s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5));
/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6));
/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6));
}
static void hmt_bl_exit(struct device *dev)
{
gpio_free(S3C64XX_GPB(4));
}
}
static struct s3c_gpio_chip gpio_4bit[] = {
{
.base = S3C64XX_GPA_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPA(0),
.ngpio = S3C64XX_GPIO_A_NR,
.label = "GPA",
},
}, {
.base = S3C64XX_GPB_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPB(0),
.ngpio = S3C64XX_GPIO_B_NR,
.label = "GPB",
},
}, {
.base = S3C64XX_GPC_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
.base = S3C64XX_GPC(0),
.ngpio = S3C64XX_GPIO_C_NR,
.label = "GPC",
},
}, {
.base = S3C64XX_GPD_BASE,
.config = &gpio_4bit_cfg_eint0111,
.chip = {
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
s3c_gpio_cfgall_range(S3C64XX_GPB(2), 2,
S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
}
static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
unsigned long iiscon;
unsigned long iismod;
unsigned long iisfcon;
unsigned int *reg_GPDCON;
unsigned int *reg_GPBCON;
reg_GPDCON = ioremap(0x7f008060,0x100);
reg_GPBCON = ioremap(0x7f008020,0x100);
s3cdbg("Entered %s\n", __FUNCTION__);
/*Set I2C port to controll WM8753 codec*/
s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_DOWN);
s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_DOWN);
s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
s3c24xx_i2s.master = 1;
/* Configure the I2S pins in correct mode */
s3c_gpio_cfgpin(S3C64XX_GPD(2),S3C64XX_GPD2_I2S0_LRCLK);
if (s3c24xx_i2s.master && !extclk){
s3cdbg("Setting Clock Output as we are Master\n");
s3c_gpio_cfgpin(S3C64XX_GPD(0),S3C64XX_GPD0_I2S0_CLK);
}
s3c_gpio_cfgpin(S3C64XX_GPD(1),S3C64XX_GPD1_I2S0_CDCLK);
s3c_gpio_cfgpin(S3C64XX_GPD(3),S3C64XX_GPD3_I2S0_DI);
s3c_gpio_cfgpin(S3C64XX_GPD(4),S3C64XX_GPD4_I2S0_DO);
/* pull-up-enable, pull-down-disable*/
s3c_gpio_setpull(S3C64XX_GPD(0), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(1), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(2), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(3), S3C_GPIO_PULL_UP);
s3c_gpio_setpull(S3C64XX_GPD(4), S3C_GPIO_PULL_UP);
s3cdbg("substream->stream : %d\n", substream->stream);
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
} else {
rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
}
/* Working copies of registers */
iiscon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0CON);
iismod = readl(s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
iisfcon = readl(s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
/* is port used by another stream */
if (!(iiscon & S3C64XX_IIS0CON_I2SACTIVE)) {
// Clear BFS field [2:1]
iismod &= ~(0x3<<1);
iismod |= S3C64XX_IIS0MOD_32FS | S3C64XX_IIS0MOD_INTERNAL_CLK;
if (!s3c24xx_i2s.master)
iismod |= S3C64XX_IIS0MOD_IMS_SLAVE;
else
iismod |= S3C64XX_IIS0MOD_IMS_EXTERNAL_MASTER;
}
/* enable TX & RX all to support Full-duplex */
iismod |= S3C64XX_IIS0MOD_TXRXMODE;
iiscon |= S3C64XX_IIS0CON_TXDMACTIVE;
iisfcon |= S3C64XX_IIS_TX_FLUSH;
iiscon |= S3C64XX_IIS0CON_RXDMACTIVE;
iisfcon |= S3C64XX_IIS_RX_FLUSH;
writel(iiscon, s3c24xx_i2s.regs + S3C64XX_IIS0CON);
writel(iismod, s3c24xx_i2s.regs + S3C64XX_IIS0MOD);
writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
// Tx, Rx fifo flush bit clear
iisfcon &= ~(S3C64XX_IIS_TX_FLUSH | S3C64XX_IIS_RX_FLUSH);
writel(iisfcon, s3c24xx_i2s.regs + S3C64XX_IIS0FIC);
s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
return 0;
}