/*
* Initialize PCI Express core
*/
int ppc440spe_init_pcie(void)
{
int time_out = 20;
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
if (check_error())
return -1;
if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
{
printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
SDR_READ(PESDR0_PLLLCT2));
return -1;
}
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
while (time_out) {
if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
time_out--;
udelay(1);
} else
break;
}
if (!time_out) {
printf("PCIE: VCO output not locked\n");
return -1;
}
return 0;
}
static void __init
yosemite_setup_arch(void)
{
uint32_t* gpio_base;
/* configuring GPIO1 for external interrupts */
gpio_base = (uint32_t*)ioremap64(PPC440EP_GPIO1_ADDR,
PPC440EP_GPIO_SIZE);
if (gpio_base) {
/* GPIO1_TCR reset bits 8-16*/
gpio_base[1] &= 0xff007fff;
/* GPIO1_TSRL reset bits 16-31*/
gpio_base[4] &= 0xffff0000;
/* GPIO1_ISR1L set bit pairs 16-17 to 30-31 to 01b*/
gpio_base[12] |= 0x5555;
/* GPIO1_TSRH reset bits 0-1*/
gpio_base[5] &= 0x3fffffff;
/* GPIO1_ISR1H set bit pair 0-1 to 01b*/
gpio_base[13] |= 0x40000000;
iounmap(gpio_base);
}
/* setting esxternal clk source for serial ports */
SDR_WRITE(DCRN_SDR_UART0, 0x800001);
SDR_WRITE(DCRN_SDR_UART1, 0x800001);
yosemite_set_emacdata();
ibm440gx_get_clocks(&clocks, YOSEMITE_SYSCLK, 6 * 1843200);
ocp_sys_info.opb_bus_freq = clocks.opb;
/* init to some ~sane value until calibrate_delay() runs */
loops_per_jiffy = 50000000/HZ;
/* Setup PCI host bridge */
yosemite_setup_hose();
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
ROOT_DEV = Root_RAM0;
else
#endif
#ifdef CONFIG_ROOT_NFS
ROOT_DEV = Root_NFS;
#else
ROOT_DEV = Root_HDA1;
#endif
yosemite_early_serial_map();
/* Identify the system */
printk( "AMCC PowerPC " BOARDNAME " Platform\n" );
}
/*
* Initialize PCI Express core as described in User Manual section 27.12.1
*/
int ppc440spe_init_pcie(void)
{
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
check_error();
printk(KERN_INFO "PCIE initialization OK\n");
if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
SDR_READ(PESDR0_PLLLCT2));
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
return 0;
}
static void __init ppc4xx_pic_impl_init(void)
{
#if defined(CONFIG_440GX)
/* Disable 440GP compatibility mode if it was enabled in firmware */
SDR_WRITE(DCRN_SDR_MFR, SDR_READ(DCRN_SDR_MFR) & ~DCRN_SDR_MFR_PCM);
#endif
/* Configure Base UIC */
mtdcr(DCRN_UIC_CR(UICB), 0);
mtdcr(DCRN_UIC_TR(UICB), 0);
mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
}
static void __init
ocotea_init_irq(void)
{
int i;
/* Enable PPC440GP interrupt compatibility mode */
SDR_WRITE(DCRN_SDR_MFR,SDR_READ(DCRN_SDR_MFR) | DCRN_SDR_MFR_PCM);
ppc4xx_pic_init();
for (i = 0; i < NR_IRQS; i++)
irq_desc[i].handler = ppc4xx_pic;
}
static void __init
luan_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
/* Enable UART2 */
SDR_WRITE(DCRN_SDR_PFC1, SDR_READ(DCRN_SDR_PFC1) | 0x01000000);
port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
port.irq = UART2_INT;
port.uartclk = clocks.uart2;
port.line = 2;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 2 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(2, &port);
#endif
}
int ppc440spe_init_pcie_rootport(int port)
{
static int core_init;
void __iomem *utl_base;
u32 val = 0;
int i;
if (!core_init) {
++core_init;
i = ppc440spe_init_pcie();
if (i)
return i;
}
/*
* Initialize various parts of the PCI Express core for our port:
*
* - Set as a root port and enable max width
* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
* - Set up UTL configuration.
* - Increase SERDES drive strength to levels suggested by AMCC.
* - De-assert RSTPYN, RSTDL and RSTGU.
*/
switch (port) {
case 0:
SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
SDR_WRITE(PESDR0_RCSSET,
(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 1:
SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR1_RCSSET,
(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 2:
SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR2_RCSSET,
(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
}
mdelay(1000);
switch (port) {
case 0: val = SDR_READ(PESDR0_RCSSTS); break;
case 1: val = SDR_READ(PESDR1_RCSSTS); break;
case 2: val = SDR_READ(PESDR2_RCSSTS); break;
}
if (!(val & (1 << 20)))
printk(KERN_INFO "PCIE%d: PGRST inactive\n", port);
else
printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val);
switch (port) {
case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break;
case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break;
case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break;
}
/*
* Map UTL registers at 0xc_1000_0n00
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
break;
case 2:
mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
}
utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100);
/*
* Set buffer allocations and then assert VRB and TXE.
*/
out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
out_be32(utl_base + PEUTL_INTR, 0x02000000);
out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
out_be32(utl_base + PEUTL_PCTL, 0x80800066);
iounmap(utl_base);
/*
* We map PCI Express configuration access into the 512MB regions
* PCIE0: 0xc_4000_0000
* PCIE1: 0xc_8000_0000
* PCIE2: 0xc_c000_0000
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
break;
case 1:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
case 2:
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
break;
}
/*
* Check for VC0 active and assert RDY.
*/
switch (port) {
case 0:
if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
break;
case 1:
if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
break;
case 2:
if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16)))
printk(KERN_WARNING "PCIE0: VC0 not active\n");
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
break;
}
#if 0
/* Dump all config regs */
for (i = 0x300; i <= 0x320; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x340; i <= 0x353; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x370; i <= 0x383; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x3a0; i <= 0x3a2; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
for (i = 0x3c0; i <= 0x3c3; ++i)
printk("[%04x] 0x%08x\n", i, SDR_READ(i));
#endif
mdelay(100);
return 0;
}
int ppc440spe_init_pcie_endport(int port)
{
static int core_init;
volatile u32 val = 0;
int attempts;
if (!core_init) {
++core_init;
if (ppc440spe_init_pcie())
return -1;
}
/*
* Initialize various parts of the PCI Express core for our port:
*
* - Set as a end port and enable max width
* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
* - Set up UTL configuration.
* - Increase SERDES drive strength to levels suggested by AMCC.
* - De-assert RSTPYN, RSTDL and RSTGU.
*
* NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
* default setting 0x11310000. The register has new fields,
* PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
* hang.
*/
switch (port) {
case 0:
SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12);
SDR_WRITE(PESDR0_UTLSET1, 0x20222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
SDR_WRITE(PESDR0_RCSSET,
(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 1:
SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR1_UTLSET1, 0x20222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR1_RCSSET,
(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 2:
SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR2_UTLSET1, 0x20222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR2_RCSSET,
(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
}
/*
* Notice: the following delay has critical impact on device
* initialization - if too short (<50ms) the link doesn't get up.
*/
mdelay(100);
switch (port) {
case 0: val = SDR_READ(PESDR0_RCSSTS); break;
case 1: val = SDR_READ(PESDR1_RCSSTS); break;
case 2: val = SDR_READ(PESDR2_RCSSTS); break;
}
if (val & (1 << 20)) {
printf("PCIE%d: PGRST failed %08x\n", port, val);
return -1;
}
/*
* Verify link is up
*/
val = 0;
switch (port)
{
case 0:
val = SDR_READ(PESDR0_LOOP);
break;
case 1:
val = SDR_READ(PESDR1_LOOP);
break;
case 2:
val = SDR_READ(PESDR2_LOOP);
break;
}
if (!(val & 0x00001000)) {
printf("PCIE%d: link is not up.\n", port);
return -1;
}
/*
* Setup UTL registers - but only on revA!
* We use default settings for revB chip.
*/
if (!ppc440spe_revB())
ppc440spe_setup_utl(port);
/*
* We map PCI Express configuration access into the 512MB regions
*
* NOTICE: revB is very strict about PLB real addressess and ranges to
* be mapped for config space; it seems to only work with d_nnnn_nnnn
* range (hangs the core upon config transaction attempts when set
* otherwise) while revA uses c_nnnn_nnnn.
*
* For revA:
* PCIE0: 0xc_4000_0000
* PCIE1: 0xc_8000_0000
* PCIE2: 0xc_c000_0000
*
* For revB:
* PCIE0: 0xd_0000_0000
* PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000
*/
switch (port) {
case 0:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
} else {
/* revA */
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
break;
case 1:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
} else {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
case 2:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
} else {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
break;
}
/*
* Check for VC0 active and assert RDY.
*/
attempts = 10;
switch (port) {
case 0:
while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE0: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
break;
case 1:
while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE1: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
break;
case 2:
while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE2: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
break;
}
mdelay(100);
return 0;
}
