//-----------------------------------------------------------------------------
static void uart_init(uint32_t baud)
{
uint64_t br = (uint64_t)65536 * (F_CPU - 16 * baud) / F_CPU;
HAL_GPIO_UART_TX_out();
HAL_GPIO_UART_TX_pmuxen(PORT_PMUX_PMUXE_C_Val);
HAL_GPIO_UART_RX_in();
HAL_GPIO_UART_RX_pmuxen(PORT_PMUX_PMUXE_C_Val);
PM->APBCMASK.reg |= PM_APBCMASK_SERCOM0;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(SERCOM0_GCLK_ID_CORE) |
GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
SERCOM0->USART.CTRLA.reg =
SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/);
SERCOM0->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/);
SERCOM0->USART.BAUD.reg = (uint16_t)br+1;
SERCOM0->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
//-----------------------------------------------------------------------------
static void uart_init(uint32_t baud)
{
HAL_GPIO_UART_TX_out();
HAL_GPIO_UART_TX_pmuxen(HAL_GPIO_PMUX_D);
HAL_GPIO_UART_RX_in();
HAL_GPIO_UART_RX_pmuxen(HAL_GPIO_PMUX_D);
MCLK->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2;
GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN;
while (0 == (GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN));
SERCOM2->USART.CTRLA.reg =
SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*INT_CLK*/) |
SERCOM_USART_CTRLA_RXPO(1/*PAD1*/) | SERCOM_USART_CTRLA_TXPO(0/*PAD0*/) |
SERCOM_USART_CTRLA_SAMPR(1);
SERCOM2->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/);
#define BAUD_VAL (F_CPU / (16 * baud))
#define FP_VAL ((F_CPU / baud - 16 * BAUD_VAL) / 2)
SERCOM2->USART.BAUD.reg =
SERCOM_USART_BAUD_FRACFP_BAUD(BAUD_VAL) |
SERCOM_USART_BAUD_FRACFP_FP(FP_VAL);
SERCOM2->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
//-----------------------------------------------------------------------------
static void uart_init(uint32_t baud)
{
uint64_t br = (uint64_t)65536 * (F_CPU - 16 * baud) / F_CPU;
HAL_GPIO_UART_TX_out();
HAL_GPIO_UART_TX_pmuxen(HAL_GPIO_PMUX_D);
HAL_GPIO_UART_RX_in();
HAL_GPIO_UART_RX_pmuxen(HAL_GPIO_PMUX_D);
MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4;
GCLK->PCHCTRL[SERCOM4_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN(0) | GCLK_PCHCTRL_CHEN;
while (0 == (GCLK->PCHCTRL[SERCOM4_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN));
SERCOM4->USART.CTRLA.reg =
SERCOM_USART_CTRLA_DORD | SERCOM_USART_CTRLA_MODE(1/*USART_INT_CLK*/) |
SERCOM_USART_CTRLA_RXPO(3/*PAD3*/) | SERCOM_USART_CTRLA_TXPO(1/*PAD2*/);
SERCOM4->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/);
SERCOM4->USART.BAUD.reg = (uint16_t)br;
SERCOM4->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate)
{
/* Calculate the BAUD value */
uint64_t temp1 = ((16 * ((uint64_t)baudrate)) << 32);
uint64_t ratio = _long_division(temp1 , UART_0_REF_F);
uint64_t scale = ((uint64_t)1 << 32) - ratio;
uint64_t baud_calculated = (65536 * scale) >> 32;
switch (uart) {
#if UART_0_EN
case UART_0:
/* Enable the peripheral channel */
GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg |= GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN_GCLK0;
while (!(GCLK->PCHCTRL[SERCOM3_GCLK_ID_CORE].reg & GCLK_PCHCTRL_CHEN)) {
/* Wait for clock synchronization */
}
MCLK->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3;
/* configure PINS to input/output*/
UART_0_PORT.DIRSET.reg = (1 << UART_0_TX_PIN); /* tx's direction is output */
UART_0_PORT.PINCFG[UART_0_RX_PIN % 32].bit.INEN = true; /* buffer rx pin's value */
/* enable PMUX for pins and set to config C. */
UART_0_PORT.WRCONFIG.reg = PORT_WRCONFIG_WRPINCFG \
| PORT_WRCONFIG_WRPMUX \
| PORT_WRCONFIG_PMUX(0x2) \
| PORT_WRCONFIG_PMUXEN \
| UART_0_PINS;
UART_0_DEV.CTRLA.bit.ENABLE = 0; //Disable to write, need to sync tho
while(UART_0_DEV.SYNCBUSY.bit.ENABLE);
/* set to LSB, asynchronous mode without parity, PAD0 Tx, PAD1 Rx,
* 16x over-sampling, internal clk */
UART_0_DEV.CTRLA.reg = SERCOM_USART_CTRLA_DORD \
| SERCOM_USART_CTRLA_FORM(0x0) \
| SERCOM_USART_CTRLA_SAMPA(0x0) \
| SERCOM_USART_CTRLA_TXPO(0x0) \
| SERCOM_USART_CTRLA_RXPO(0x1) \
| SERCOM_USART_CTRLA_SAMPR(0x0) \
| SERCOM_USART_CTRLA_MODE(0x1) \
| (UART_0_RUNSTDBY ? SERCOM_USART_CTRLA_RUNSTDBY : 0);
/* Set baud rate */
UART_0_DEV.BAUD.bit.BAUD = baud_calculated;
/* enable receiver and transmitter, one stop bit*/
UART_0_DEV.CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
while(UART_0_DEV.SYNCBUSY.bit.CTRLB);
break;
#endif
}
uart_poweron(uart);
return 0;
}
void SERCOM::initPads(SercomUartTXPad txPad, SercomRXPad rxPad)
{
//Setting the CTRLA register
sercom->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(txPad) |
SERCOM_USART_CTRLA_RXPO(rxPad);
// Enable Transceiver and Receiver
sercom->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN | SERCOM_USART_CTRLB_RXEN ;
}
uint32_t serial_find_mux_settings (serial_t *obj)
{
/* Sanity check arguments */
MBED_ASSERT(obj);
uint32_t mux_setting = 0;
uint32_t pinpad[4] = {0};
uint8_t i = 0;
uint32_t sercom_index = pinmap_merge_sercom(pSERIAL_S(obj)->pins[0], pSERIAL_S(obj)->pins[1]);
for (i = 0; i < 4 ; i++) {
pinpad[i] = pinmap_pad_sercom(pSERIAL_S(obj)->pins[i], sercom_index);
}
switch(pinpad[USART_RX_INDEX]) {
case 0:
mux_setting |= SERCOM_USART_CTRLA_RXPO(0);
break;
case 1:
mux_setting |= SERCOM_USART_CTRLA_RXPO(1);
break;
case 2:
mux_setting |= SERCOM_USART_CTRLA_RXPO(2);
break;
case 3:
mux_setting |= SERCOM_USART_CTRLA_RXPO(3);
break;
}
if ((pSERIAL_S(obj)->pins[USART_RXFLOW_INDEX] == NC) && (pSERIAL_S(obj)->pins[USART_TXFLOW_INDEX] == NC)) {
if (pinpad[USART_TX_INDEX] == 0) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(0);
} else if(pinpad[USART_TX_INDEX] == 2) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(1);
} else {
}
} else { // for hardware flow control and uart // expecting the tx in pad 0, rts in pad2 and cts in pad 3
if((pinpad[USART_TX_INDEX] == 0) && (pinpad[USART_RXFLOW_INDEX]/*rts pin*/ == 2) && (pinpad[USART_TXFLOW_INDEX] /*cts pin*/ == 3)) {
mux_setting |= SERCOM_USART_CTRLA_TXPO(2);
}
}
return mux_setting;
}
static int init_base(uart_t uart, uint32_t baudrate)
{
uint32_t baud;
SercomUsart *dev;
if ((unsigned int)uart >= UART_NUMOF) {
return -1;
}
/* get the devices base register */
dev = _uart(uart);
/* calculate baudrate */
baud = ((((uint32_t)CLOCK_CORECLOCK * 10) / baudrate) / 16);
/* enable sync and async clocks */
uart_poweron(uart);
/* configure pins */
gpio_init(uart_config[uart].rx_pin, GPIO_IN);
gpio_init_mux(uart_config[uart].rx_pin, uart_config[uart].mux);
gpio_init(uart_config[uart].tx_pin, GPIO_OUT);
gpio_init_mux(uart_config[uart].tx_pin, uart_config[uart].mux);
/* reset the UART device */
dev->CTRLA.reg = SERCOM_USART_CTRLA_SWRST;
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) {}
/* set asynchronous mode w/o parity, LSB first, TX and RX pad as specified
* by the board in the periph_conf.h, x16 sampling and use internal clock */
dev->CTRLA.reg = (SERCOM_USART_CTRLA_DORD |
SERCOM_USART_CTRLA_SAMPR(0x1) |
SERCOM_USART_CTRLA_TXPO(uart_config[uart].tx_pad) |
SERCOM_USART_CTRLA_RXPO(uart_config[uart].rx_pad) |
SERCOM_USART_CTRLA_MODE_USART_INT_CLK);
/* set baudrate */
dev->BAUD.FRAC.FP = (baud % 10);
dev->BAUD.FRAC.BAUD = (baud / 10);
/* enable receiver and transmitter, use 1 stop bit */
dev->CTRLB.reg = (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
while (dev->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) {}
/* finally, enable the device */
dev->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
return 0;
}
// ****************************************************************************
void HAL_uart_init(uint32_t baudrate)
{
#define UART_CLK 48000000
uint64_t brr = (uint64_t)65536 * (UART_CLK - 16 * baudrate) / UART_CLK;
// Use GLKGEN0 (48 MHz) as clock source for the UART
GCLK->CLKCTRL.reg =
GCLK_CLKCTRL_ID(UART_SERCOM_GCLK_ID) |
GCLK_CLKCTRL_CLKEN |
GCLK_CLKCTRL_GEN(0);
// Run UART from GCLK; Setup Rx and Tx pads
UART_SERCOM->USART.CTRLA.reg =
SERCOM_USART_CTRLA_DORD |
SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
SERCOM_USART_CTRLA_RXPO(HAL_GPIO_RX.rxpo) |
SERCOM_USART_CTRLA_TXPO(tx_pad);
// Enable transmit and receive; 8 bit characters
UART_SERCOM->USART.CTRLB.reg =
SERCOM_USART_CTRLB_RXEN |
SERCOM_USART_CTRLB_TXEN |
SERCOM_USART_CTRLB_CHSIZE(0); // 8 bits
while (UART_SERCOM->USART.SYNCBUSY.reg);
UART_SERCOM->USART.BAUD.reg = (uint16_t)brr;
while (UART_SERCOM->USART.SYNCBUSY.reg);
UART_SERCOM->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
while (UART_SERCOM->USART.SYNCBUSY.reg);
// Enable the receive interrupt
UART_SERCOM->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC;
NVIC_EnableIRQ(UART_SERCOM_IRQN);
}
void uart_init(uint32_t baud) {
uint32_t UART_CLKGEN_F = 8000000UL;
uint64_t br = (uint64_t)65536 * (UART_CLKGEN_F - 16 * baud) / UART_CLKGEN_F;
//enable GPS pins
// SaLPinMode(MTK3339_RX_PIN,INPUT);
// SaLPinMode(MTK3339_TX_PIN,OUTPUT);
SYSCTRL->OSC8M.reg -= SYSCTRL_OSC8M_ENABLE;
SYSCTRL->OSC8M.reg -= SYSCTRL_OSC8M_PRESC_3;
SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE;
//portB22->PINCFG->reg = 0x44;
// portB23->PINCFG->reg = 0x44;
// GPS pin configs
((Port *)PORT)->Group[1].PINCFG[22].reg = 0x41;
((Port *)PORT)->Group[1].PINCFG[23].reg = 0x41;
((Port *)PORT)->Group[1].PMUX[11].reg = 0x32;
// usb port configs
// ((Port *)PORT)->Group[0].PINCFG[24].reg = 0x41;
// ((Port *)PORT)->Group[0].PINCFG[25].reg = 0x41;
// ((Port *)PORT)->Group[0].PMUX[12].reg = 0x24;
//enable power to sercom 5 module
PM->APBCMASK.reg |= PM_APBCMASK_SERCOM5;
//enable and configure the sercom clock
GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) |
GCLK_GENDIV_DIV(1);
GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(3) |
GCLK_GENCTRL_SRC_OSC8M |
GCLK_GENCTRL_IDC |
GCLK_GENCTRL_RUNSTDBY |
GCLK_GENCTRL_GENEN;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM5_CORE |
GCLK_CLKCTRL_GEN_GCLK3 |
GCLK_CLKCTRL_CLKEN;
// GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOMX_SLOW |
// GCLK_CLKCTRL_GEN_GCLK3 |
// GCLK_CLKCTRL_CLKEN;
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_SERCOM3_CORE |
GCLK_CLKCTRL_GEN_GCLK3 |
GCLK_CLKCTRL_CLKEN;
//configure the sercom module for the gps (sercom 5)
SERCOM5->USART.CTRLA.reg = SERCOM_USART_CTRLA_DORD |
SERCOM_USART_CTRLA_MODE_USART_INT_CLK |
SERCOM_USART_CTRLA_RXPO(3) |
SERCOM_USART_CTRLA_TXPO(1);
uart_sync(SERCOM5);
SERCOM5->USART.CTRLB.reg = SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN |
SERCOM_USART_CTRLB_CHSIZE(0/*8 bits*/);
// SERCOM_USART_CTRLB_SFDE;
uart_sync(SERCOM5);
SERCOM5->USART.BAUD.reg = (uint16_t)br;
uart_sync(SERCOM5);
SERCOM5->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE;
uart_sync(SERCOM5);
SaLInitUsart(&USART_0,SERCOM5);
}
