int main ( int argc, char **argv )
{
int status, length;
io_channel chan;
struct rpc_msg msg;
char *CApath=NULL,*CAfile=NULL;
int badop=0;
int ret=1;
int client_auth=0;
int server_auth=0;
SSL_CTX *s_ctx=NULL;
/*
* Confirm logical link with initiating client.
*/
LIB$INIT_TIMER();
status = SYS$ASSIGN ( &sysnet, &chan, 0, 0, 0 );
printf("status of assign to SYS$NET: %d\n", status );
/*
* Initialize standard out and error files.
*/
if (bio_err == NULL)
if ((bio_err=BIO_new(BIO_s_file())) != NULL)
BIO_set_fp(bio_err,stderr,BIO_NOCLOSE);
if (bio_stdout == NULL)
if ((bio_stdout=BIO_new(BIO_s_file())) != NULL)
BIO_set_fp(bio_stdout,stdout,BIO_NOCLOSE);
/*
* get the preferred cipher list and other initialization
*/
if (cipher == NULL) cipher=getenv("SSL_CIPHER");
printf("cipher list: %s\n", cipher ? cipher : "{undefined}" );
SSL_load_error_strings();
OpenSSL_add_all_algorithms();
/* DRM, this was the original, but there is no such thing as SSLv2()
s_ctx=SSL_CTX_new(SSLv2());
*/
s_ctx=SSL_CTX_new(SSLv2_server_method());
if (s_ctx == NULL) goto end;
SSL_CTX_use_certificate_file(s_ctx,TEST_SERVER_CERT,SSL_FILETYPE_PEM);
SSL_CTX_use_RSAPrivateKey_file(s_ctx,TEST_SERVER_CERT,SSL_FILETYPE_PEM);
printf("Loaded server certificate: '%s'\n", TEST_SERVER_CERT );
/*
* Take commands from client until bad status.
*/
LIB$SHOW_TIMER();
status = doit ( chan, s_ctx );
LIB$SHOW_TIMER();
/*
* do final cleanup and exit.
*/
end:
if (s_ctx != NULL) SSL_CTX_free(s_ctx);
LIB$SHOW_TIMER();
return 1;
}
void lowlevel_init(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
#if defined(CONFIG_SPEAR1310) && !defined(CONFIG_SPEAR1380_REVC)
u32 pad_dir_sel1_reg;
#endif
/* Pad configuration */
#ifdef CONFIG_SPEAR1380_REVC
/* bootrom IO are routed and driven by IPs in standard part.
* To avoid contention on Spear output driven and other device on board
* IO are routed to RAS and not driven because RAS part is always under reset
*
* IOs routed to standard IPs:
* EGPIO_A[0],..EGPIO_A[7],EGPIO_B[8],EGPIO_B[9]
* SDA,SCL
* SMIDATAIN,SMIDATAOUT,SMI_CLK,SMI_nCS[0],SMI_nCS[1]
* NFIO[0],..,NFIO[7],NFCE0,NFWE,NFRE,NFALE,NFCLE,NFRB,NFRWPRT0
* GMII_TXCLK125,GMII_TXCLK,MII_TXCLK,TXD[0],TXD[1],TXD[2],TXD[3],GMII_TXD[4],GMII_TXD[5],GMII_TXD[6],GMII_TXD[7],TX_EN,TX_ER
* RX_CLK,RX_DV,RX_ER,RXD[0],RXD[1],RXD[2],RXD[3],GMII_RXD[4],GMII_RXD[5],GMII_RXD[6],GMII_RXD[7],GMII_COL,CRS,MDC,MDIO
* MCI_Data0,MCI_Data1_SD,MCI_Data2_SD,MCI_Data3_SD,MCI_Addr1_CLE_CLK,MCI_nCD_SD_MMC,MCI_DMARQ_RnB_WP,MCI_SD_CMD
*
* Others configurable IOs are configured for RAS.
*
* use Table 60 in SPEAR1310 - ADDRESS MAP AND REGISTERS RM - REV2.pdf
*
*/
/* pad function enable :
* 0 : pad routed to RAS
* 1 : pad routed to IP
*/
writel( 0x1 /* bit 0 is reserved in revC */
| (0x1 << 2) /* SDA, SCL */
| (0x3ff << 6) /* EGPIO_A[0],..EGPIO_A[7],EGPIO_B[8],EGPIO_B[9] */
| (0x1 << 16) /* SMIDATAIN,SMIDATAOUT,SMI_CLK,SMI_nCS[0],SMI_nCS[1] */
| (0x1 << 17) /* FSMC for NAND 8-bit */
| (0x1f << 18) /* MAC0 */
, &misc_p->pad_function_en_1);
writel(((0x1 << 27)) /* MCI_Data0 */
, &misc_p->pad_function_en_2);
writel( (0x7 << 3) /* MCI_Data1_SD,MCI_Data2_SD,MCI_Data3_SD */
| (0x1 << 7) /* MCI_Addr1_CLE_CLK */
| (0x1 << 15) /* MCI_nCD_SD_MMC */
| (0x1 << 17) /* MCI_DMARQ_RnB_WP */
| (0x1 << 26) /* MCI_SD_CMD */
, &misc_p->pad_function_en_3);
/* pad direction selection :
* 0 : pad direction set to input
* 1 : pad direction controlled by IP or RAS depending on pad_function_en_* registers
*/
writel( 0xfffffffe, &misc_p->pad_dir_sel_1); // bit 0 reserved
writel( 0xffffffff, &misc_p->pad_dir_sel_2);
writel( 0x7fffffff, &misc_p->pad_dir_sel_3); // bit 31 reserved
/* pad pull up and pull down configuration : done in OS */
/* pad drive level configuration : done in OS */
/* pad slew level configuration : done in OS */
#endif
/* Initialize PLLs */
sys_init();
#if defined(CONFIG_OS_BOOT)
writel(readl(&misc_p->perip1_clk_enb) | UART_CLKEN,
&misc_p->perip1_clk_enb);
#endif
/* Enable IPs (release reset) */
writel(PERIPH1_RST_ALL, &misc_p->perip1_sw_rst);
writel(PERIPH2_RST_ALL, &misc_p->perip2_sw_rst);
#if defined(CONFIG_SPEAR900_LCAD) || defined(CONFIG_SPEAR1340_LCAD)
pl061_init();
/* Power on complete */
set_lcad_power_on();
#endif
#if defined(CONFIG_SPEAR1340)
writel(PERIPH3_RST_ALL, &misc_p->perip3_sw_rst);
#else
writel(RAS_RST_ALL, &misc_p->ras_sw_rst);
#endif
#if defined(CONFIG_SPEAR1310) && !defined(CONFIG_SPEAR1380_REVC)
pad_dir_sel1_reg = readl(&misc_p->pad_dir_sel_1);
pad_dir_sel1_reg |= PAD_DIR_SEL_1_UART;
writel(pad_dir_sel1_reg, &misc_p->pad_dir_sel_1);
#endif
/* Read Ras Gpio for hardware configuration bits of MPMC*/
#ifdef CONFIG_SPEAR1380_REVC
/* init uart debug */
spear_serial_init();
/* Configure ras clock, reset, and pads to access RGPIO2B pins
* used to read hardware configuration bits */
struct conf_regs *conf = (struct conf_regs *)CONFIG_RAS_CONF_BASE;
u32 perip1_clk_enb;
u32 ras_clk_enb;
/* enable CLK periph 1 */
perip1_clk_enb = readl(&misc_p->perip1_clk_enb);
perip1_clk_enb |= (0x1 ); // enable bus (ahb axi) clk
perip1_clk_enb |= (GPIO1_CLKEN); // enable clk for gpio B used for test mode detection
writel(perip1_clk_enb, &misc_p->perip1_clk_enb);
/* enable 166Mhz, 83Mhz, 48Mhz and 30Mkz clock for RAS. */
ras_clk_enb = 0x1 | 0x1 << 1 | 0x1 << 5 | 0x1 << 6;
writel(ras_clk_enb, &misc_p->ras_clk_enb);
/* disable protection */
writel(DIS_PROT_WORD, &conf->prot_dis);
/* configure ROW[5:2] pad = hardware configuration bits */
u32 regIO = readl(&conf->IO23);
regIO = (regIO & (~((u32)(0xffff) << 16)))
| (RAS_PAD_FUNC7 << 16) /* ROW[2] */
| (RAS_PAD_FUNC7 << 20) /* ROW[3] */
| (RAS_PAD_FUNC7 << 24) /* ROW[4] */
| (RAS_PAD_FUNC7 << 28); /* ROW[5] */
writel(regIO, &conf->IO23);
/* enable protection */
writel(EN_PROT_WORD, &conf->prot_en);
readl(&conf->prot_en);
#ifdef DEBUG_TRACK_DDR_INIT
uartDebug_Puts("\r\n");
uartDebug_Puts("pad conf to rd hw conf 16 or 32 bit ddr : OK\r\n");
#endif
#endif
pll_late_init();
/* Initialize MPMC */
RESET_TIMER;
mpmc_init();
SHOW_TIMER("mpmc_init");
#ifdef DEBUG_TRACK_DDR_INIT
uartDebug_Puts("mpmc_init : OK\r\n");
#endif
/* SoC specific initialization */
soc_init();
#ifdef DEBUG_TRACK_DDR_INIT
uartDebug_Puts("soc_init : OK\r\n");
#endif
#ifdef CONFIG_RAM_TEST
/* WARNING: must wait few time before accessing DDR */
/* process test for DDR */
RESET_TIMER;
test_ddr(TEST_DDR_WITHOUT_ECC);
SHOW_TIMER("test_ddr_no_ecc");
#ifdef DEBUG_TRACK_DDR_INIT
uartDebug_Puts("test_ddr wo ECC: OK\r\n");
#endif
#endif
}