/* Timer read/write register */ static void ep9312_tc_read (u32 offset, u32 * data, int index) { if (index == 4) { if (offset == TC_VALUELOW) *data = io.tc[index].load; else if (offset == TC_VALUEHIGH) *data = io.tc[index].value; } switch (offset) { case TC_LOAD: *data = io.tc[index].load; break; case TC_VALUE: *data = io.tc[index].value; break; case TC_CTL: *data = io.tc[index].ctl; break; case TC_CLEAR: SKYEYE_DBG ("%s(0x%x, 0x%x): read WO register\n", __func__, offset, data); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } }
static void s3c2440_uart_write (ARMul_State * mstate, u32 offset, u32 data) { SKYEYE_DBG ("s3c2440_uart_write(0x%x, 0x%x)\n", offset, data); switch (offset) { case ULCON: io.uart0.ulcon = data; break; case UCON: io.uart0.ucon = data; break; case UFCON: io.uart0.ufcon = data; break; case UMCON: io.uart0.umcon = data; break; case UTRSTAT: io.uart0.utrstat = data; break; case UERSTAT: io.uart0.uerstat = data; break; case UFSTAT: io.uart0.ufstat = data; break; case UMSTAT: io.uart0.umstat = data; break; case UTXH: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.uart0.utrstat |= 0x6; //set strstat register bit[0] if ((io.uart0.ucon & 0xc) == 0x4) { s3c2440_set_subsrcint (UART_INT_TXD << (0 * 3)); extern ARMul_State *state; s3c2440_update_int (state); } } break; case UBRDIV: io.uart0.ubrdiv = data; break; default: break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); }
static void ns9750_uart_write (void *state, u32 offset, u32 data) { SKYEYE_DBG ("ns9750_uart_write(0x%x, 0x%x)\n", offset, data); switch (offset) { case US_CR: io.uart0.cr = data; break; case US_MR: io.uart0.mr = data; break; case US_IER: //io.uart0.ier = data; io.uart0.imr |= (data & 0x000f3fff); if (io.uart0.imr) { io.ipr |= AT91RM92_ID_US0; ns9750_update_int (state); } break; case US_IDR: /* disable usart0 corresponding interrupt * */ io.uart0.imr &= (~data) & 0x000f3fff; break; case US_THR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.uart0.csr |= AT91RM92_US_TXRDY; } //io.uart0.thr = data; break; case US_BRGR: io.uart0.brgr = data; break; case US_RTOR: io.uart0.rtor = data; break; case US_TTGR: io.uart0.ttgr = data; break; case US_FIDI: io.uart0.fidi = data; break; case US_IF: io.uart0.us_if = data; break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); }
static uint32_t ns9750_io_read_word (void *state, uint32_t addr) { uint32_t data = -1; int i; /*uart0 */ if ((addr >= AT91RM92_UART_BASE0) && (addr < (AT91RM92_UART_BASE0 + AT91RM92_UART_SIZE))) { ns9750_uart_read ((u32) (addr - AT91RM92_UART_BASE0), (u32 *) & data); } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { ns9750_st_read ((u32) (addr - AT91RM92_ST_BASE0), (u32 *) & data); } switch (addr) { case AIC_IVR: /* IVR */ data = io.ipr; SKYEYE_DBG ("IVR irqs=%x ", data); for (i = 0; i < 32; i++) if (data & (1 << i)) break; if (i < 32) { data = i; io.ipr &= ~(1 << data); ns9750_update_int (state); } else data = 0; io.ivr = data; SKYEYE_DBG ("read IVR=%d\n", data); break; case AIC_ISR: /* ISR: interrupt status register */ data = io.ivr; break; case AIC_IMR: /* IMR */ data = io.imr; break; case AIC_CISR: /* CISR: Core interrupt status register */ data = io.cisr; data = io.imr; SKYEYE_DBG ("read CISR=%x,%x\n", data, io.cisr); break; default: break; } return data; }
static void ns9750_io_write_word (void *state, uint32_t addr, uint32_t data) { if ((addr >= AT91RM92_UART_BASE0) && (addr < AT91RM92_UART_BASE0 + AT91RM92_UART_SIZE)) { ns9750_uart_write (state, addr - AT91RM92_UART_BASE0, data); } if ((addr >= AT91RM92_ST_BASE0) && (addr < (AT91RM92_ST_BASE0 + AT91RM92_ST_SIZE))) { ns9750_st_write (state, addr - AT91RM92_ST_BASE0, data); } switch (addr) { case AIC_IECR: /* IECR */ io.iecr = data; io.imr |= data; break; case AIC_IDCR: /* IDCR */ io.idcr = data; io.imr &= ~data; break; case AIC_ICCR: /* CLEAR interrupts */ io.iccr = data; io.ipr &= ~data; break; case AIC_EOICR: /* EOI */ io.eoicr = data; io.ipr &= ~data; ns9750_update_int (state); break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } }
void ep9312_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; if ((addr >= EP9312_TC_BASE1) && (addr < (EP9312_TC_BASE1 + EP9312_TC_SIZE))) { ep9312_tc_write (state, (u32) (addr - EP9312_TC_BASE1), data, 0); } if ((addr >= EP9312_UART_BASE1) && (addr < (EP9312_UART_BASE1 + EP9312_UART_SIZE))) { ep9312_uart_write (state, (u32) (addr - EP9312_UART_BASE1), data, 0); } if ((addr >= EP9312_UART_BASE3) && (addr < (EP9312_UART_BASE3 + EP9312_UART_SIZE))) { ep9312_uart_write (state, (u32) (addr - EP9312_UART_BASE3), data, 2); } switch (addr) { case SYSCON_CLKSET1: break; case SYSCON_CLKSET2: case SYSCON_PWRCNT: break; case VIC0INTENABLE: io.intmr[0] = data; if (data != 0x10 && data != 0x20) printf ("SKYEYE: write VIC0INTENABLE=0x%x\n", data); extern ARMul_State * state; ep9312_update_int (state); break; case VIC1INTENABLE: io.intmr[1] = data; // printf("SKYEYE: write VIC1INTENABLE=0x%x\n", data); extern ARMul_State * state; ep9312_update_int (state); break; case VIC0INTENCLEAR: io.intmr[0] ^= data; extern ARMul_State * state; ep9312_update_int (state); break; case VIC1INTENCLEAR: io.intmr[1] ^= data; extern ARMul_State * state; ep9312_update_int (state); break; case SYSCON_DEVCFG: io.syscon_devcfg = data; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x, 0x%08x), pc %x \n", __func__, addr, data, state->Reg[15]); break; } }
static void ep9312_uart_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case UART_DR: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } case UART_RSR: //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: { io.uart[index].cr = data; if ((data & AMBA_UARTCR_TIE) == 0) { io.intmr[0] &= ~(UART_TXINTR[index]); io.intsr[0] &= ~(UART_TXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.intmr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~(UART_IIR_TIS); //Interrupt Identification and Clear } else { io.intmr[0] |= (UART_TXINTR[index]); io.intsr[0] |= (UART_TXINTR[index]); io.intsr[1] = (INT_UART[index]); io.intmr[1] = (INT_UART[index]); io.uart[index].iir |= (UART_IIR_TIS); } extern ARMul_State * state; ep9312_update_int (state); } break; case UART_FR: case UART_IIR: io.uart[index].iir = data; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); } }
void coldfire_step_once () { unsigned int Instr; struct _Instruction *InstructionPtr; #ifdef INSTRUCTION_PROFILE unsigned long long LowTime=0, HighTime=0; char Buffer[16]; #endif //while(!Run_Exit) { if(1){ SKYEYE_DBG("New cycle, PC=0x%08lx, SP=0x%08lx\n", memory_core.pc, memory_core.a[7]); /* printf("New cycle, PC=0x%08lx, SP=0x%08lx\n", memory_core.pc, memory_core.a[7]); */ /* Check for any pending exceptions */ exception_check_and_handle(); /* As we're coming back from an interrupt, check for exit */ //if(Run_Exit) break; /* Save the PC for the beginning of this instruction * This is useful for exceptions that reset the PC */ memory_core.pc_instruction_begin = memory_core.pc; /* Before we execute this instruction, catch a bad PC counter */ /* Get the instruction from memory */ if(!Memory_RetrWord(&Instr, memory_core.pc)) //continue; ; /* Look it up */ InstructionPtr = Instruction_FindInstruction(Instr); if(InstructionPtr==NULL) { //exception_do_exception(4); //continue; } else { /* Run the instruction */ (*InstructionPtr->FunctionPtr)(); } /* Now update anything that could cause an interrupt, so we * can catch it in the next cycle */ /* Call this, which will call an update * for things like the UARTs and Timers */ //skyeye_config.mach->mach_io_do_cycle (&memory_core); exec_callback(); } }
static void ep9312_tc_write (ARMul_State * state, u32 offset, u32 data, int index) { switch (offset) { case TC_LOAD: io.tc[index].load = data; break; case TC_VALUE: SKYEYE_DBG ("%s(0x%x, 0x%x): write RO register\n", __func__, offset, data); break; case TC_CTL: io.tc[index].ctl = data; break; case TC_CLEAR: io.intsr[0] &= ~TCOI[index]; extern ARMul_State * state; ep9312_update_int (state); break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } }
static void ep9312_uart_read (ARMul_State * state, u32 offset, u32 * data, int index) { switch (offset) { case UART_DR: *data = io.uart[index].dr; io.uart[index].dr = 0; io.intsr[0] &= ~(UART_RXINTR[index]); io.intsr[1] &= ~(INT_UART[index]); io.uart[index].iir &= ~UART_IIR_RIS; io.uart[index].fr |= UART_FR_RXFE; extern ARMul_State* state; ep9312_update_int (state); break; case UART_RSR: *data = io.uart[index].rsr; break; //case UART_ECR: case UART_CR_H: case UART_CR_M: case UART_CR_L: break; case UART_CR: *data = io.uart[index].cr; break; case UART_FR: *data = io.uart[index].fr; break; case UART_IIR: *data = io.uart[index].iir; break; //case UART_ICR: case UART_ILPR: case UART_DMACR: case UART_TCR: case UART_TISR: case UART_TOCR: case UART_TMR: case UART_MCR: case UART_MSR: break; default: SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); break; } }
static void s3c2440_io_write_word (void* arch_instance, ARMword addr, ARMword data) { extern ARMul_State *state; if ((addr >= UART_CTL_BASE0) && (addr < UART_CTL_BASE0 + UART_CTL_SIZE)) { s3c2440_uart_write (state, addr - UART_CTL_BASE0, data); } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2440_timer_write (state, addr - PWM_CTL_BASE, data); } switch (addr) { case SRCPND: io.srcpnd &= (~data & INT_MASK_INIT); s3c2440_update_int(state); break; case INTMOD: io.intmod = data; break; case INTMSK: io.intmsk = data; s3c2440_update_int (state); break; case PRIORITY: io.priority = data; break; case INTPND: io.intpnd &= (~data & INT_MASK_INIT); io.intoffset = 0; //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x, pc:%x\n", io.intoffset, io.intpnd, addr, data, state->pc); break; /*read only */ //case INTOFFSET: // break; case SUBSRCPND: io.subsrcpnd &= (~data & INT_SUBMSK_INIT); break; case INTSUBMSK: io.intsubmsk = data; break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); break; } }
static void s3c2410x_uart_read (u32 offset, u32 * data, int index) { switch (offset) { case ULCON: *data = io.uart[index].ulcon; break; case UCON: *data = io.uart[index].ucon; break; case UFCON: *data = io.uart[index].ufcon; break; case UMCON: *data = io.uart[index].umcon; break; case UTRSTAT: *data = io.uart[index].utrstat; break; case UERSTAT: *data = io.uart[index].uerstat; break; case UFSTAT: *data = io.uart[index].ufstat; break; case UMSTAT: *data = io.uart[index].umstat; break; case URXH: /* receive char * */ *data = io.uart[index].urxh; io.uart[index].utrstat &= (~0x1); /* clear strstat register bit[0] */ io.uart[index].ufstat &= ~(0x1); /* 2007-02-09 by Anthony Lee : for 0 bytes */ break; case UBRDIV: *data = io.uart[index].ubrdiv; break; default: break; } SKYEYE_DBG ("%s(UART%d: 0x%x, 0x%x)\n", __FUNCTION__, index, offset, data); }
static void s3c2440_uart_read (u32 offset, u32 * data) { switch (offset) { case ULCON: *data = io.uart0.ulcon; break; case UCON: *data = io.uart0.ucon; break; case UFCON: *data = io.uart0.ufcon; break; case UMCON: *data = io.uart0.umcon; break; case UTRSTAT: *data = io.uart0.utrstat; break; case UERSTAT: *data = io.uart0.uerstat; break; case UFSTAT: *data = io.uart0.ufstat; break; case UMSTAT: *data = io.uart0.umstat; break; case URXH: /* receive char * */ *data = io.uart0.urxh; io.uart0.utrstat &= (~0x1); /* clear strstat register bit[0] */ io.uart0.ufstat &= ~(0x1); break; case UBRDIV: *data = io.uart0.ubrdiv; break; default: break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); }
static void ns9750_uart_read (u32 offset, u32 *data) { switch (offset) { case US_MR: *data = io.uart0.mr; break; case US_IMR: *data = io.uart0.imr; break; case US_CSR: *data = io.uart0.csr; break; case US_RHR: /* receive char * */ *data = io.uart0.rhr; io.uart0.csr &= (~AT91RM92_US_RXRDY); break; case US_BRGR: *data = io.uart0.brgr; break; case US_RTOR: *data = io.uart0.rtor; break; case US_TTGR: *data = io.uart0.ttgr; break; case US_FIDI: *data = io.uart0.fidi; break; case US_NER: *data = io.uart0.ner; break; case US_IF: *data = io.uart0.us_if; break; } SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data); }
static void s3c2440_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2440_io_write_halfword error\n"); s3c2440_io_write_word (state, addr, data); }
static void s3c2410x_io_write_byte (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: s3c2410x_io_write_byte error\n"); s3c2410x_io_write_word (state, addr, data); }
static void s3c2410x_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { if ((addr >= UART_CTL_BASE0) && (addr < UART_CTL_BASE0 + UART_CTL_SIZE)) { s3c2410x_uart_write (state, (addr - UART_CTL_BASE0) % 0x4000, data, (addr - UART_CTL_BASE0) / 0x4000); return; } if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) { s3c2410x_timer_write (state, addr - PWM_CTL_BASE, data); return; } /* * 2007-02-09 by Anthony Lee * changed 0xC0 to 0xA4 for running linux-2.6.20, * because GSTATUS1 is 0xB0, the "0xC0" make it like S3C2400 */ if((addr >= GPIO_CTL_BASE) && (addr < (GPIO_CTL_BASE + 0xA4))){ int offset = addr - GPIO_CTL_BASE; io.gpio_ctl[offset] = data; return; } switch (addr) { case SRCPND: io.srcpnd &= (~data & INT_MASK_INIT); //2006-04-04 chy, for eCos on s3c2410. SRCPND will change the INTPND, INTOFFSET, so when write SRCPND, the interrupt should be update extern ARMul_State * state; s3c2410x_update_int (state); break; case INTMOD: io.intmod = data; break; case INTMSK: io.intmsk = data; extern ARMul_State * state; s3c2410x_update_int (state); break; case PRIORITY: io.priority = data; break; case INTPND: io.intpnd &= (~data & INT_MASK_INIT); io.intoffset = 0; //printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x, pc:%x\n", io.intoffset, io.intpnd, addr, data, state->pc); break; /*read only */ //case INTOFFSET: // break; case SUBSRCPND: io.subsrcpnd &= (~data & INT_SUBMSK_INIT); break; case INTSUBMSK: io.intsubmsk = data; break; /* ext interrupt */ case EINTMASK: io.eintmask = data; break; case EINTPEND: io.eintpend &= (~data & 0x00FFFFF0); break; case CLKCON: io.clkpower.clkcon = data; break; case CLKSLOW: io.clkpower.clkslow = data; break; case CLKDIVN: io.clkpower.clkdivn = data; break; case BWSCON: io.memctl.bwscon = data; break; case MPLLCON: io.clkpower.mpllcon = data; break; case BANKCON0: io.memctl.bankcon[0] = data; break; case BANKCON1: io.memctl.bankcon[1] = data; break; case BANKCON2: io.memctl.bankcon[2] = data; break; case BANKCON3: io.memctl.bankcon[3] = data; break; case BANKCON4: io.memctl.bankcon[4] = data; break; case BANKCON5: io.memctl.bankcon[5] = data; break; case BANKCON6: io.memctl.bankcon[6] = data; break; case BANKCON7: io.memctl.bankcon[7] = data; break; case REFRESH: io.memctl.refresh = data; break; case BANKSIZE: io.memctl.banksize = data; break; case MRSRB6: io.memctl.mrsrb6 = data; break; case MRSRB7: io.memctl.mrsrb7 = data; break; case WDCON: io.wd_timer.wtcon = data; break; case WDDAT: io.wd_timer.wtdat = data; break; case WDCNT: io.wd_timer.wtcnt = data; break; default: SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data); fprintf(stderr, "ERROR: %s(0x%08x) = 0x%08x\n", __FUNCTION__, addr ,data); break; } }
void ep9312_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); }
ARMword ep9312_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = 0; /* TC1 */ if ((addr >= EP9312_TC_BASE1) && (addr < (EP9312_TC_BASE1 + EP9312_TC_SIZE))) { ep9312_tc_read ((u32) (addr - EP9312_TC_BASE1), (u32 *) & data, 0); } /* TC2 */ if ((addr >= EP9312_TC_BASE4) && (addr < (EP9312_TC_BASE4 + EP9312_TC_SIZE))) { ep9312_tc_read ((u32) (addr - EP9312_TC_BASE4), (u32 *) & data, 3); } /* UART1 */ if ((addr >= EP9312_UART_BASE1) && (addr < (EP9312_UART_BASE1 + EP9312_UART_SIZE))) { ep9312_uart_read (state, (u32) (addr - EP9312_UART_BASE1), (u32 *) & data, 0); return data; } /* UART3 */ if ((addr >= EP9312_UART_BASE3) && (addr < (EP9312_UART_BASE3 + EP9312_UART_SIZE))) { ep9312_uart_read (state, (u32) (addr - EP9312_UART_BASE3), (u32 *) & data, 2); return data; } switch (addr) { case SYSCON_PWRCNT: break; case VIC0INTENABLE: data = io.intmr[0]; // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case VIC0IRQSTATUS: data = io.intsr[0]; io.intsr[0] = 0; //!!! break; case VIC1IRQSTATUS: data = io.intsr[1]; io.intsr[1] = 0; break; case RTCDR: case AACGCR: case AACRGIS: // printf("%s(0x%08x) = 0x%08x\n", __func__, addr, data); break; case SYSCON_DEVCFG: data = io.syscon_devcfg; break; default: SKYEYE_DBG ("SKYEYE:unknown io addr, %s(0x%08x) = 0x%08x\n", __func__, addr, data); break; } return data; }
ARMword ep9312_io_read_halfword (ARMul_State * state, ARMword addr) { SKYEYE_DBG ("SKYEYE: %s error\n", __func__); }
} void s3c4510b_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { switch (addr) { case SYSCFG: io.syscfg = data; break; case CLKCON: io.clkcon = data; break; case INTMOD: io.intmod = data; break; case INTPND: /*when write bit 1, we clear apropiate pendind bit. * */ io.intpnd &= (~data & INT_MASK_INIT); break; case INTMSK: io.intmsk = data; break; case INTOFFSET: case INTPNDTST: io.intpndtst = io.intpnd = data; break; case INTOSET_FIQ: io.intoset_fiq = data; break; case INTOSET_IRQ: io.intoset_irq = data; break; /*UART*/ case ULCON0: io.ulcon0 = data; break; case ULCON1: io.ulcon1 = data; break; case UCON0: io.ucon0 = data; break; case UCON1: io.ucon1 = data; break; case USTAT0: io.ustat0 = data; break; case USTAT1: io.ustat1 = data; break; case UTXBUF0: { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); io.ustat0 |= (UART_LSR_THRE | UART_LSR_TEMT); if ((io.ucon0 & 0xc) == 0xc) { /*enable interrupt */ s3c4510b_set_interrupt (INT_UARTTX0); extern ARMul_State * state; s3c4510b_update_int (state); } } break; case UTXBUF1: break; case UBRDIV0: io.ubrdiv0 = data; break; case UBRDIV1: io.ubrdiv1 = data; break; /*Timer */ case TMOD: io.tmod = data; if (ENABLE_TIMER0) io.tcnt0 = io.tdata0; if (ENABLE_TIMER1) io.tcnt1 = io.tdata1; break; case TDATA0: if (!ENABLE_TIMER0) io.tdata0 = data; /*we manually set tdata0 register, uclinux's data is so big */ io.tdata0 = 0xfff; break; case TDATA1: //if (!ENABLE_TIMER1) io.tdata1 = data; break; case TCNT0: io.tcnt0 = data; break; case TCNT1: io.tcnt1 = data; break; default: SKYEYE_DBG ("%s(0x%08x) = 0x%08x\n", __FUNCTION__, addr, data); break; } }
void ep7312_io_write_word (void *state, uint32_t addr, uint32_t data) { uint32_t tmp; switch (addr - 0x80000000) { case SYSCON: tmp = io.syscon; io.syscon = data; //chy 2004-03-11 if ((tmp & LCDEN) != (data & LCDEN)) { // by ywc 2004-07-07 printf ("\n\n SYSCON:will call ep7312_update_lcd()"); //ep7312_update_lcd (state); } break; case SYSFLG: break; case INTSR: //DBG_PRINT("write INTSR=0x%x\n", data); io.intsr = data; // printf("SKYEYE: write INTSR=0x%x\n", io.intsr); break; case INTMR: //DBG_PRINT("write INTMR=0x%x\n", data); //if(data != 0x2000 && data != 0x2200) //printf("SKYEYE: write INTMR=0x%x\n", data); io.intmr = data; ep7312_update_int (state); break; case TC1D: io.tcd[0] = io.tcd_reload[0] = data & 0xffff; SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff); break; case TC2D: io.tcd[1] = io.tcd_reload[1] = data & 0xffff; SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff); break; case UARTDR: /* The UART writes chars to console */ { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; /* case BLEOI: printf("BLEOI\n"); break; case MCEOI: printf("MCEOI\n"); break; case TEOI: printf("TEOI\n"); break;*/ case TC1EOI: io.intsr &= ~TC1OI; ep7312_update_int (state); SKYEYE_DBG ("TC1EOI\n"); break; case TC2EOI: io.intsr &= ~TC2OI; ep7312_update_int (state); SKYEYE_DBG ("TC2EOI\n"); break; //case RTCEOI: printf("RTCEOI\n"); break; //case UMSEOI: printf("UMSEOI\n"); break; //case COEOI: printf("COEOI\n"); break; case 0x2000: /* Not a real register, for debugging only: */ SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data); break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //printf("SKYEYE:unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]); break; } }
static uint32_t ns9750_io_read_halfword (void *state, uint32_t addr) { SKYEYE_DBG ("SKYEYE: ns9750_io_read_halfword error\n"); ns9750_io_read_word (state, addr); }
static void ns9750_io_write_halfword (void *state, uint32_t addr, uint32_t data) { SKYEYE_DBG ("SKYEYE: ns9750_io_write_halfword error\n"); ns9750_io_write_word (state, addr, data); }
void cs89712_io_write_word (ARMul_State * state, ARMword addr, ARMword data) { ARMword tmp; switch (addr - 0x80000000) { case SYSCON: tmp = io.syscon; io.syscon = data; /*if ((tmp & LCDEN) != (data & LCDEN)) { update_lcd(state); } */ break; case SYSFLG: break; case INTSR: break; case INTMR: io.intmr = data; extern ARMul_State * state; cs89712_update_int (state); break; case LCDCON: tmp = io.lcdcon; io.lcdcon = data; if ((tmp & (VBUFSIZ | LINELEN | GSEN | GSMD)) != (tmp & (VBUFSIZ | LINELEN | GSEN | GSMD))) { //chy 2005-01-07 no use now /* update_lcd(state); */ } break; case TC1D: io.tcd[0] = io.tcd_reload[0] = data & 0xffff; SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff); break; case TC2D: io.tcd[1] = io.tcd_reload[1] = data & 0xffff; SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff); break; case UARTDR: /* The UART writes chars to console */ { char c = data; /* 2007-01-18 modified by Anthony Lee : for new uart device frame */ skyeye_uart_write(-1, &c, 1, NULL); } break; /* case BLEOI: printf("BLEOI\n"); break; case MCEOI: printf("MCEOI\n"); break; case TEOI: printf("TEOI\n"); break;*/ case TC1EOI: io.intsr &= ~TC1OI; extern ARMul_State * state; cs89712_update_int (state); SKYEYE_DBG ("TC1EOI\n"); break; case TC2EOI: io.intsr &= ~TC2OI; extern ARMul_State * state; cs89712_update_int (state); SKYEYE_DBG ("TC2EOI\n"); break; //case RTCEOI: printf("RTCEOI\n"); break; //case UMSEOI: printf("UMSEOI\n"); break; //case COEOI: printf("COEOI\n"); break; case 0x2000: /* Not a real register, for debugging only: */ SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data); break; default: //chy 2003-07-11: sometime has fault, but linux can continue running !!!!???? //printf("unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]); break; } }
ARMword s3c4510b_io_read_word (ARMul_State * state, ARMword addr) { ARMword data = -1; switch (addr) { case SYSCFG: data = io.syscfg; break; case CLKCON: data = io.clkcon; break; case INTMOD: data = io.intmod; break; case INTPND: data = io.intpnd; break; case INTMSK: data = io.intmsk; break; case INTOFFSET: case INTPNDTST: data = io.intpndtst; break; case INTOSET_FIQ: data = io.intoset_fiq; break; case INTOSET_IRQ: { /*find which interrupt is pending */ int i; for (i = 0; i < 26; i++) { if (io.intpnd & (1 << i)) break; } if (i < 26) { data = (i << 2); } else data = 0x54; /*no interrupt is pending, 0x54 is init data. */ } //data = io.intoset_irq; break; /*UART*/ case ULCON0: data = io.ulcon0; break; case ULCON1: data = io.ulcon1; break; case UCON0: data = io.ucon0; break; case UCON1: data = io.ucon1; break; case USTAT0: data = io.ustat0; io.ustat0 &= ~0xf; break; case USTAT1: data = io.ustat1; io.ustat1 &= ~0xf; break; //case UTXBUF0: //case UTXBUF1: case URXBUF0: data = io.urxbuf0; io.ustat0 &= ~UART_LSR_DR; break; case URXBUF1: data = io.urxbuf1; io.ustat1 &= ~UART_LSR_DR; break; case UBRDIV0: data = io.ubrdiv0; break; case UBRDIV1: data = io.ubrdiv1; break; /*Timer */ case TMOD: data = io.tmod; break; case TDATA0: data = io.tdata0; break; case TDATA1: data = io.tdata1; break; case TCNT0: data = io.tcnt0; break; case TCNT1: data = io.tcnt1; break; default: SKYEYE_DBG ("%s (addr = 0x%08x)\n", __FUNCTION__, addr); break; } return data; }