char ROM_BYTE_Write(unsigned int addr, unsigned char leng, unsigned char Write_data_in) { unsigned char data_in[1]; int err; data_in[0] = Write_data_in; err = SMB_Write(addr, leng, data_in); // Delay for IIC_SPEED_400KHZ udelay(38);//Delay_us(38); return err; }
static int EEPROM_EnterWriteMode_write(unsigned int addr, unsigned int length, unsigned char *DATA) { unsigned char eep_data = 0; if(ROM_BYTE_Write(EEPPAG0, 1, (unsigned char) (EEP_WEN | addr)) != TRUE) // page0 addr write (low addr) return -5; I2C_DELAY(); if(ROM_BYTE_Write(EEPPAG1, 1, (unsigned char) (EEP_WEN | (addr >> 7))) != TRUE) // page1 addr write (high addr) return -6; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_LOAD1) != TRUE) // load1 command return -7; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_LOAD2) != TRUE) // load2 command return -8; I2C_DELAY(); if(SMB_Write(0, length, DATA) != TRUE) // data write return -9; if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_ERPRG) != TRUE) // erase & programming return -10; I2C_DELAY(); do{ if(ROM_BYTE_Read(EEPCFG, 1, &eep_data) != TRUE) // check ready bit return -11; I2C_DELAY(); }while((eep_data & 0x01) != EEPRDY); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_STNBY) != TRUE) // stnby mode return -12; I2C_DELAY(); return TRUE; }
int EEPROM_EraseAll() { int addr = 0; unsigned char eep_data = 0; if(ROM_BYTE_Write(EEPPROT, 1, 0x9F) != TRUE) // Protection register UNLOCK! return -1; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_STNBY) != TRUE) // stnby mode (added by kyi) return -2; I2C_DELAY(); if(ROM_BYTE_Write(EEPMODE, 1, EEP_WEN | ALL_PAGE_ERASE) != TRUE) // eeprom main mode access return -3; I2C_DELAY(); if(ROM_BYTE_Write(EEPCFG, 1, EEP_WEN | AUTOADR) != TRUE) // eeprom main mode access return -3; I2C_DELAY(); if(ROM_BYTE_Write(EEPPAG0, 1, (unsigned char) (EEP_WEN | 0)) != TRUE) // eeprom main mode access return -4; I2C_DELAY(); if(ROM_BYTE_Write(EEPPAG1, 1, (unsigned char) (EEP_WEN | (0 >> 7))) != TRUE) // eeprom main mode access return -5; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_LOAD1) != TRUE) // eeprom main mode access return -6; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_LOAD2) != TRUE) // eeprom main mode access return -7; I2C_DELAY(); if(SMB_Write(0, EEP_PAGE_SIZE, &eep_data) != TRUE) // data write return -8; I2C_DELAY(); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_ERPRG) != TRUE) // eeprom main mode access return -9; I2C_DELAY(); do { if(ROM_BYTE_Read(EEPCFG, 1, &eep_data) != TRUE) // eeprom main mode access return -10; I2C_DELAY(); } while((eep_data & 0x01) != EEPRDY); if(ROM_BYTE_Write(EEPCOMM, 1, EEP_WENL | EEP_STNBY) != TRUE) // eeprom main mode access return -11; I2C_DELAY(); if(ROM_BYTE_Write(EEPMODE, 1, EEP_WEN | MAIN_MODE) != TRUE) // eeprom main mode access return -12; I2C_DELAY(); if(ROM_BYTE_Write(EEPPROT, 1, EEP_WEN | 0x00) != TRUE) // protection register LCOK! return -13; I2C_DELAY(); return TRUE; }
//----------------------------------------------------------------------------- // MAIN Routine //----------------------------------------------------------------------------- // // Main routine performs all configuration tasks, then loops forever sending // and receiving SMBus data to the slave <SLAVE_ADDR>. // void main (void) { unsigned char odoslat[4] = {0x00,0x00,0x12,0xFF}; volatile unsigned char dat; // Test counter unsigned char i; // Dummy variable counters PCA0MD &= ~0x40; // WDTE = 0 (watchdog timer enable bit) OSCICN |= 0x07; // Set internal oscillator to highest // setting of 24500000 // If slave is holding SDA low because of an improper SMBus reset or error while(!SDA) { // Provide clock pulses to allow the slave to advance out // of its current state. This will allow it to release SDA. XBR1 = 0x40; // Enable Crossbar SCL = 0; // Drive the clock low for(i = 0; i < 255; i++); // Hold the clock low SCL = 1; // Release the clock while(!SCL); // Wait for open-drain // clock output to rise for(i = 0; i < 10; i++); // Hold the clock high XBR1 = 0x00; // Disable Crossbar } Port_Init (); // Initialize Crossbar and GPIO Timer1_Init (); // Configure Timer1 for use as SMBus // clock source Timer3_Init (); // Configure Timer3 for use with SMBus // low timeout detect SMBus_Init (); // Configure and enable SMBus EIE1 |= 0x01; // Enable the SMBus interrupt LED = 0; EA = 1; // Global interrupt enable // TEST CODE------------------------------------------------------------------- dat = 0; // Output data counter NUM_ERRORS = 0; // Error counter while (1) { // SMBus Write Sequence if (dat < 4){ SMB_DATA_OUT = odoslat[dat]; // Define next outgoing byte TARGET = SLAVE_ADDR; // Target the F3xx/Si8250 Slave for next // SMBus transfer SMB_Write(); // Initiate SMBus write } // SMBus Read Sequence // TARGET = SLAVE_ADDR; // Target the F3xx/Si8250 Slave for next // SMBus transfer //SMB_Read(); // Check transfer data /*if(SMB_DATA_IN != SMB_DATA_OUT) // Received data match transmit data? { NUM_ERRORS++; // Increment error counter if no match }*/ // Indicate that an error has occurred (LED no longer lit) if (NUM_ERRORS > 0) { LED = 0; } else { LED = ~LED; } // Run to here to view the SMB_DATA_IN and SMB_DATA_OUT variables dat++; T0_Wait_ms (1); // Wait 1 ms until the next cycle } // END TEST CODE--------------------------------------------------------------- }