Exemplos de SMC_REG_ID_SFR_W em C++ (Cpp)

Exemplo n.º 1

Arquivo: tmu-exynos.c Projeto: EthanRS/Odroid-X2-Android-OS-4.1-Kernel

void set_refresh_rate(unsigned int auto_refresh)
{
	/*
	 * uRlk = FIN / 100000;
	 * refresh_usec =  (unsigned int)(fMicrosec * 10);
	 * uRegVal = ((unsigned int)(uRlk * uMicroSec / 100)) - 1;
	*/
	pr_debug("@@@ set_auto_refresh = 0x%02x\n", auto_refresh);

#ifdef CONFIG_ARCH_EXYNOS4
#ifdef CONFIG_ARM_TRUSTZONE
	exynos_smc(SMC_CMD_REG,
		SMC_REG_ID_SFR_W((EXYNOS4_PA_DMC0_4212 + TIMING_AREF_OFFSET)),
		auto_refresh, 0);
	exynos_smc(SMC_CMD_REG,
		SMC_REG_ID_SFR_W((EXYNOS4_PA_DMC1_4212 + TIMING_AREF_OFFSET)),
		auto_refresh, 0);
#else
	/* change auto refresh period in TIMING_AREF register of dmc0  */
	__raw_writel(auto_refresh, S5P_VA_DMC0 + TIMING_AREF_OFFSET);

	/* change auto refresh period in TIMING_AREF regisger of dmc1 */
	__raw_writel(auto_refresh, S5P_VA_DMC1 + TIMING_AREF_OFFSET);
#endif
#endif	/* CONFIG_ARCH_EXYNOS4 */
}

Exemplo n.º 2

Arquivo: tmu-exynos.c Projeto: droidroidz/Manta_kernel

static void set_refresh_period(unsigned int freq_ref,
				unsigned int refresh_nsec)
{
	unsigned int rclk, auto_refresh;

	rclk = freq_ref / 1000000;
	auto_refresh = ((unsigned int)(rclk * refresh_nsec / 1000));

	/* change auto refresh period in TIMING_AREF register of DMC */
#if defined(CONFIG_ARM_TRUSTZONE)
	exynos_smc(SMC_CMD_REG,
		SMC_REG_ID_SFR_W(EXYNOS5_PA_DREXII + EXYNOS_DMC_TIMINGAREF_OFFSET),
		auto_refresh, 0);
#else
	__raw_writel(auto_refresh, S5P_VA_DREXII +
			EXYNOS_DMC_TIMING_AREF_OFFSET);
#endif
}

Exemplo n.º 3

Arquivo: exynos3470_thermal.c Projeto: DJSteve/g800f_custom_kernel

static void exynos_memory_auto_refresh(unsigned long event, void *v)
{
	switch (event) {
#ifdef CONFIG_ARM_TRUSTZONE
		case TMU_THR_LV1:
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4X12 + DREX_TIMINGAREF),
					AREF_NORMAL, 0);
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4X12 + DREX_TIMINGAREF),
					AREF_NORMAL, 0);
			break;
		case TMU_THR_LV2:
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4X12 + DREX_TIMINGAREF),
					AREF_HOT, 0);
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4X12 + DREX_TIMINGAREF),
					AREF_HOT, 0);
			break;
		case TMU_THR_LV3:
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC0_4X12 + DREX_TIMINGAREF),
					AREF_CRITICAL, 0);
			exynos_smc(SMC_CMD_REG, SMC_REG_ID_SFR_W(EXYNOS4_PA_DMC1_4X12 + DREX_TIMINGAREF),
					AREF_CRITICAL, 0);
			break;
#else
		case TMU_THR_LV1:
			__raw_writel(AREF_NORMAL,(exynos4_base_drex0 + DREX_TIMINGAREF));
			__raw_writel(AREF_NORMAL,(exynos4_base_drex1 + DREX_TIMINGAREF));
			break;
		case TMU_THR_LV2:
			__raw_writel(AREF_HOT,(exynos4_base_drex0 + DREX_TIMINGAREF));
			__raw_writel(AREF_HOT,(exynos4_base_drex1 + DREX_TIMINGAREF));
			break;
		case TMU_THR_LV3:
			__raw_writel(AREF_CRITICAL,(exynos4_base_drex0 + DREX_TIMINGAREF));
			__raw_writel(AREF_CRITICAL,(exynos4_base_drex1 + DREX_TIMINGAREF));
			break;
#endif
	}
}