void SpiCC3000DMAInit(void)
{
NVIC_InitTypeDef NVIC_RxInt_InitStructure;
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
DMA_DeInit(SPI_DMA_RX_CHANNEL);
DMA_DeInit(SPI_DMA_TX_CHANNEL);
/* Configure and enable SPI DMA TX Channel interrupt */
NVIC_RxInt_InitStructure.NVIC_IRQChannel = DMA1_Channel3_IRQn;
NVIC_RxInt_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_RxInt_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_RxInt_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_RxInt_InitStructure);
/* Enable the DMA Channels Interrupts */
DMA_ITConfig(SPI_DMA_TX_CHANNEL, DMA_IT_TC, ENABLE); //传输完成中断打开
DMA_ITConfig(SPI_DMA_RX_CHANNEL, DMA_IT_TC, ENABLE);
/* Configure DMA Peripheral but don't send data*/
CC3000_DMA_Config(SPI_DMA_RX, (uint8_t*)wlan_rx_buffer,0);
CC3000_DMA_Config(SPI_DMA_TX, (uint8_t*)wlan_tx_buffer,0);
/* Enable SPI DMA request */
SPI_I2S_DMACmd(SPI_BASE,SPI_I2S_DMAReq_Rx, ENABLE);
SPI_I2S_DMACmd(SPI_BASE,SPI_I2S_DMAReq_Tx, ENABLE);
/* Enable DMA RX Channel */
DMA_Cmd(SPI_DMA_RX_CHANNEL, ENABLE);
/* Enable DMA TX Channel */
DMA_Cmd(SPI_DMA_TX_CHANNEL, ENABLE);
}
void hal_spi_c::init_dma_(void)
{
#if 0
// Enable DMA interface clock
RCC_AHB1PeriphClockCmd(SPI1_MASTER_DMA_CLK, ENABLE);
SPI_I2S_DMACmd(SPI1_MASTER, SPI_I2S_DMAReq_Tx, ENABLE); // подключаем ПДП к SPI_ТX
SPI_I2S_DMACmd(SPI1_MASTER, SPI_I2S_DMAReq_Rx, ENABLE); // подключаем ПДП к SPI_RX
// включаем прерывания DMA_SPI
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
NVIC_InitTypeDef NVICx;
NVICx.NVIC_IRQChannel = SPI1_MASTER_Rx_DMA1_IRQ;
NVICx.NVIC_IRQChannelPreemptionPriority = 1;
NVICx.NVIC_IRQChannelSubPriority = 0;
NVICx.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVICx);
NVICx.NVIC_IRQChannel = SPI1_MASTER_IRQ;
NVICx.NVIC_IRQChannelPreemptionPriority = 0;
NVICx.NVIC_IRQChannelSubPriority = 0;
NVICx.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVICx);
#endif
}
/**
* Prepare the system to watch for a HSYNC pulse to trigger the pixel
* clock and clock out the next line
*/
static void prepare_line(uint32_t line_num)
{
if (line_num < GRAPHICS_HEIGHT) {
uint32_t buf_offset = line_num * GRAPHICS_WIDTH;
dev_cfg->pixel_timer.timer->CNT = dc;
DMA_ClearFlag(dev_cfg->mask.dma.tx.channel, DMA_FLAG_TCIF7 | DMA_FLAG_HTIF7 | DMA_FLAG_FEIF7 | DMA_FLAG_TEIF7);
DMA_ClearFlag(dev_cfg->level.dma.tx.channel, DMA_FLAG_FEIF5 | DMA_FLAG_TEIF5);
// Load new line
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel, (uint32_t)&disp_buffer_level[buf_offset], DMA_Memory_0);
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel, (uint32_t)&disp_buffer_mask[buf_offset], DMA_Memory_0);
// Enable DMA, Slave first
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel, BUFFER_LINE_LENGTH);
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel, BUFFER_LINE_LENGTH);
SPI_Cmd(dev_cfg->level.regs, ENABLE);
SPI_Cmd(dev_cfg->mask.regs, ENABLE);
/* Enable SPI interrupts to DMA */
SPI_I2S_DMACmd(dev_cfg->mask.regs, SPI_I2S_DMAReq_Tx, ENABLE);
SPI_I2S_DMACmd(dev_cfg->level.regs, SPI_I2S_DMAReq_Tx, ENABLE);
DMA_Cmd(dev_cfg->level.dma.tx.channel, ENABLE);
DMA_Cmd(dev_cfg->mask.dma.tx.channel, ENABLE);
}
reset_hsync_timers();
}
/**
* @brief Pauses or Resumes the audio stream playing from the Media.
* @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different
* from 0) to resume.
* @param Addr: Address from/at which the audio stream should resume/pause.
* @retval None
*/
static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr)
{
/* Pause the audio file playing */
if (Cmd == AUDIO_PAUSE)
{
/* Disable the I2S DMA request */
SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE);
/* Pause the I2S DMA Stream
Note. For the STM32F40x devices, the DMA implements a pause feature,
by disabling the stream, all configuration is preserved and data
transfer is paused till the next enable of the stream.
This feature is not available on STM32F40x devices. */
DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
}
else /* AUDIO_RESUME */
{
/* Enable the I2S DMA request */
SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
/* Resume the I2S DMA Stream
Note. For the STM32F40x devices, the DMA implements a pause feature,
by disabling the stream, all configuration is preserved and data
transfer is paused till the next enable of the stream.
This feature is not available on STM32F40x devices. */
DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE);
/* If the I2S peripheral is still not enabled, enable it */
if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0)
{
I2S_Cmd(CODEC_I2S, ENABLE);
}
}
}
// READ (done)
int dmaRcvBytes(SPI_TypeDef *SPIx, void *rbuf, unsigned count, int half) {
DMA_InitTypeDef DMA_InitStructure;
uint16_t dummy[] = {0xffff};
DMA_DeInit(DMA1_Channel4);
DMA_DeInit(DMA1_Channel5);
// Common to both channels
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(SPIx->DR));
DMA_InitStructure.DMA_PeripheralDataSize = (half) ? DMA_PeripheralDataSize_HalfWord : DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = (half) ? DMA_MemoryDataSize_HalfWord : DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_BufferSize = count;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
// Rx Channel
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)rbuf;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_Init(DMA1_Channel4, &DMA_InitStructure);
// Tx channel
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) dummy;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
// Enable channels
DMA_Cmd(DMA1_Channel4, ENABLE);
DMA_Cmd(DMA1_Channel5, ENABLE);
// Enable SPI TX/RX request
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
// Wait for completion
while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET);
// Disable channels
DMA_Cmd(DMA1_Channel4, DISABLE);
DMA_Cmd(DMA1_Channel5, DISABLE);
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);
return count;
}
void dma1_c4_irq_handler(void) {
DMA_ITConfig(DMA1_Channel4, DMA_IT_TC, DISABLE);
/* Disable SPI_2 Rx and TX request */
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, DISABLE);
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
/* Disable DMA1 Channel4 and 5 */
DMA_Cmd(DMA1_Channel4, DISABLE);
DMA_Cmd(DMA1_Channel5, DISABLE);
switch (sc18is600.transaction) {
case Sc18Is600ReadRegister:
case Sc18Is600WriteRegister:
sc18is600.status = Sc18Is600TransactionComplete;
Sc18Is600Unselect();
break;
case Sc18Is600Transmit:
if (sc18is600.status==Sc18Is600SendingRequest) {
sc18is600.status = Sc18Is600WaitingForI2C;
Sc18Is600Unselect();
}
else if (sc18is600.status == Sc18Is600ReadingI2CStat) {
sc18is600.i2c_status = sc18is600.priv_rx_buf[2];
sc18is600.status = Sc18Is600TransactionComplete;
Sc18Is600Unselect();
}
break;
case Sc18Is600Receive:
case Sc18Is600Transcieve:
if (sc18is600.status==Sc18Is600SendingRequest) {
sc18is600.status = Sc18Is600WaitingForI2C;
Sc18Is600Unselect();
}
else if (sc18is600.status == Sc18Is600ReadingI2CStat) {
sc18is600.status = Sc18Is600ReadingBuffer;
sc18is600.priv_tx_buf[0] = Sc18Is600_Cmd_Read_Buffer;
// debug
for (int i=1; i<sc18is600.rx_len+1; i++) sc18is600.priv_tx_buf[i] = 0;
Sc18Is600Select();
sc18is600_setup_SPI_DMA(sc18is600.rx_len+1);
}
else if (sc18is600.status == Sc18Is600ReadingBuffer) {
sc18is600.status = Sc18Is600TransactionComplete;
Sc18Is600Unselect();
}
break;
default:
break;
}
}
void MSPI_Write_Dma(const uint8_t *txb,uint8_t *rxb,uint16_t size,uint8_t incopt)
{
dummy = 0;
if (!txb) txb = (uint8_t *)&dummy;
if (!rxb) rxb = (uint8_t *)&dummy;
/* SPIx_Rx_DMA_Channel configuration ---------------------------------*/
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPIx_DR_Base;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)rxb;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStructure.DMA_BufferSize = size;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = (incopt & SPIDMAINC_RxInc)? DMA_MemoryInc_Enable: DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_Init(SPIx_Rx_DMA_Channel, &DMA_InitStructure);
/* SPIx_Tx_DMA_Channel configuration ---------------------------------*/
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)SPIx_DR_Base;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)txb;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_MemoryInc = (incopt & SPIDMAINC_TxInc)? DMA_MemoryInc_Enable: DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
DMA_Init(SPIx_Tx_DMA_Channel, &DMA_InitStructure);
DMA_ClearITPendingBit(SPIx_Tx_DMA_CLR_Pendings);
DMA_ClearITPendingBit(SPIx_Rx_DMA_CLR_Pendings);
sema_clear(xSemaSpi);
/* Enable Rx DMA Channel Transfer Complete interrupt */
DMA_ITConfig(SPIx_Rx_DMA_Channel, DMA_IT_TC, ENABLE);
/* Enable Tx DMA Channel Transfer Complete interrupt */
// DMA_ITConfig(SPIx_Tx_DMA_Channel, DMA_IT_TC, ENABLE);
/* Enable SPI DMA Rx request */
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx, ENABLE);
/* Enable SPI DMA Tx request */
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Tx, ENABLE);
/* Enable DMA Rx Channel transfer */
DMA_Cmd(SPIx_Rx_DMA_Channel, ENABLE);
/* Enable DMA Tx Channel transfer */
DMA_Cmd(SPIx_Tx_DMA_Channel, ENABLE);
xSemaphoreTake(xSemaSpi,portMAX_DELAY);
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Tx, DISABLE);
DMA_Cmd(SPIx_Tx_DMA_Channel, DISABLE);
}
void initDmaSpi2()
{
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
//TX
DMA_InitTypeDef dmaInit;
dmaInit.DMA_BufferSize = 2;
dmaInit.DMA_Channel = DMA_Channel_0;
dmaInit.DMA_DIR = DMA_DIR_MemoryToPeripheral;
dmaInit.DMA_FIFOMode = DMA_FIFOMode_Disable;
dmaInit.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
dmaInit.DMA_Memory0BaseAddr = (uint32_t)flashBuffOut;
dmaInit.DMA_MemoryBurst = DMA_MemoryBurst_Single;
dmaInit.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
dmaInit.DMA_MemoryInc = DMA_MemoryInc_Enable;
dmaInit.DMA_Mode = DMA_Mode_Normal;
dmaInit.DMA_PeripheralBaseAddr = (uint32_t)&(SPI2->DR);
dmaInit.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
dmaInit.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dmaInit.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dmaInit.DMA_Priority = DMA_Priority_Medium;
DMA_Init(DMA1_Stream4, &dmaInit);
NVIC_EnableIRQ(DMA1_Stream4_IRQn);
DMA_ITConfig(DMA1_Stream4, DMA_IT_TC, ENABLE);
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
//RX
dmaInit.DMA_BufferSize = 2;
dmaInit.DMA_Channel = DMA_Channel_0;
dmaInit.DMA_DIR = DMA_DIR_PeripheralToMemory;
dmaInit.DMA_FIFOMode = DMA_FIFOMode_Disable;
dmaInit.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
dmaInit.DMA_Memory0BaseAddr = (uint32_t)flashBuffIn;
dmaInit.DMA_MemoryBurst = DMA_MemoryBurst_Single;
dmaInit.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
dmaInit.DMA_MemoryInc = DMA_MemoryInc_Enable;
dmaInit.DMA_Mode = DMA_Mode_Normal;
dmaInit.DMA_PeripheralBaseAddr = (uint32_t)&(SPI2->DR);
dmaInit.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
dmaInit.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
dmaInit.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dmaInit.DMA_Priority = DMA_Priority_Medium;
DMA_Init(DMA1_Stream3, &dmaInit);
NVIC_EnableIRQ(DMA1_Stream3_IRQn);
DMA_ITConfig(DMA1_Stream3, DMA_IT_TC, ENABLE);
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx, ENABLE);
}
// data in buffer will be sent and will be overwritten with
// the data read back from the spi slave
void hal_spi_dma_xfer(uint8_t *buffer, uint8_t len) {
//debug("xfer "); debug_put_uint8(len); debug(")\n");
// TX: transfer buffer to slave
CC25XX_SPI_TX_DMA_CHANNEL->CMAR = (uint32_t)buffer;
CC25XX_SPI_TX_DMA_CHANNEL->CNDTR = len;
// RX: read back data from slave
CC25XX_SPI_RX_DMA_CHANNEL->CMAR = (uint32_t)buffer;
CC25XX_SPI_RX_DMA_CHANNEL->CNDTR = len;
// enable both dma
DMA_Cmd(CC25XX_SPI_RX_DMA_CHANNEL, ENABLE);
DMA_Cmd(CC25XX_SPI_TX_DMA_CHANNEL, ENABLE);
//debug("DMA EN\n"); debug_flush();
// trigger the SPI TX + RX dma
SPI_I2S_DMACmd(CC25XX_SPI, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
//debug("TRIG\n"); debug_flush();
#if 0
// Wait until the command is sent to the DR
while (!DMA_GetFlagStatus(CC25XX_SPI_TX_DMA_TC_FLAG)) {};
//debug("ACTIVE\n"); debug_flush();
// wait for tx to be finished:
while (DMA_GetFlagStatus(CC25XX_SPI_TX_DMA_TC_FLAG)) {};
while (DMA_GetFlagStatus(CC25XX_SPI_RX_DMA_TC_FLAG)) {};
//wait for SPI to be no longer busy
while (SPI_I2S_GetFlagStatus(CC25XX_SPI, SPI_I2S_FLAG_BSY) != RESET){}
//debug("!BUSY\n"); debug_flush();
#endif
while (SPI_I2S_GetFlagStatus(CC25XX_SPI, SPI_I2S_FLAG_TXE) == RESET);
while (SPI_I2S_GetFlagStatus(CC25XX_SPI, SPI_I2S_FLAG_BSY) != RESET){}
//while((SPI1->SR & 2) == 0); // wait while TXE flag is 0 (TX is not empty)
//while((SPI1->SR & (1 << 7)) != 0); // wait while BSY flag is 1 (SPI is busy)
//disable DMA
DMA_Cmd(CC25XX_SPI_RX_DMA_CHANNEL, DISABLE);
DMA_Cmd(CC25XX_SPI_TX_DMA_CHANNEL, DISABLE);
// clear DMA flags
SPI_I2S_DMACmd(CC25XX_SPI,SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);
}
/**
* @brief DMA_I2S_Configuration 配置DMA总线
* @param addr:数据源地址
* @param size:要传输的数据大小
* @retval none
*/
void DMA_I2S_Configuration(uint32_t addr, uint32_t size)
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel5_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;//?????(0 ??)
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;//????(0 ??)
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
/* DMA 通道配置*/
DMA_Cmd(DMA1_Channel5, DISABLE);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(SPI2->DR)); //目的地址，iis的数据寄存器
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = size;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
//DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE);//????DMA???
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE); //使能DMA请求
}
/*******************************************************************************
* Function Name : INTR_RXSTSQLVL_ISODU_Callback
* Description : Rx FIFO Status Queue Level, Data Update interrupt callback routine.
* Input : None.
* Output : None.
* Return : None.
*******************************************************************************/
void INTR_RXSTSQLVL_ISODU_Callback(void)
{
/* Check if the USB transfer has reached the half of the global buffer */
if(IsocBufferIdx == (NUM_SUB_BUFFERS / 2))
{
/* Check if the DMA is already enabled or not */
if ((DMA1_Channel5->CCR & 0x1) == 0x0)
{
/* Re-Initialize the number of data to be transferred */
DMA1_Channel5->CNDTR = (uint16_t)((ISOC_BUFFER_SZE * NUM_SUB_BUFFERS) / 2);
/* Enable DMA1 Channel5 */
DMA_Cmd(DMA1_Channel5, ENABLE);
/* Enable I2S DMA request for TX */
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, ENABLE);
/* Enable the I2S cell */
I2S_Cmd(SPI2, ENABLE);
}
/* Wait till the TC flag is ON (direct register access to optimize time) */
while (((DMA1->ISR & (uint32_t)0x00020000) == 0))
{}
/* Clear All DMA1 channel 5 flags */
DMA_ClearFlag(DMA1_FLAG_GL5);
}
}
// Starts a DMA transfer to OLED
static void oled_dma(uint8_t *data, uint32_t count) {
DMA2_Stream3->CR = stream_cr;
DMA2_Stream3->NDTR = count;
DMA2_Stream3->M0AR = (uint32_t)data;
DMA_Cmd(DMA2_Stream3, ENABLE);
SPI_I2S_DMACmd(OLED_SPI, SPI_I2S_DMAReq_Tx, ENABLE);
}
void SPI_TxDma_Config(void)
{
DMA_InitTypeDef DMA_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
DMA_Cmd(DMA1_Stream7, DISABLE);
DMA_DeInit(DMA1_Stream7);
DMA_InitStructure.DMA_Channel = DMA_Channel_0;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(SPI3->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = 0;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = 0;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA1_Stream7, &DMA_InitStructure);
DMA_Cmd(DMA1_Stream7, ENABLE);
SPI_I2S_DMACmd(SPI3, SPI_I2S_DMAReq_Tx, ENABLE);
}
/**
* @brief Initializes the Audio Codec audio interface (I2S)
* @note This function assumes that the I2S input clock (through PLL_R in
* Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y)
* is already configured and ready to be used.
* @param AudioFreq: Audio frequency to be configured for the I2S peripheral.
* @retval None.
*/
static void Codec_AudioInterface_Init(uint32_t AudioFreq)
{
/* Enable the CODEC_I2S peripheral clock */
RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE);
RCC->APB1ENR |= RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3;
/* CODEC_I2S peripheral configuration */
SPI_I2S_DeInit(CODEC_I2S);
I2S_InitStructure.I2S_AudioFreq = AudioFreq;
I2S_InitStructure.I2S_Standard = I2S_STANDARD;
I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b;
I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low;
I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx;
#ifdef CODEC_MCLK_ENABLED
I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable;
#elif defined(CODEC_MCLK_DISABLED)
I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable;
#else
#error "No selection for the MCLK output has been defined !"
#endif /* CODEC_MCLK_ENABLED */
/* Initialize the I2S peripheral with the structure above */
I2S_Init(CODEC_I2S, &I2S_InitStructure);
/* Enable the I2S DMA TX request */
SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
/* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function
or by user functions if DMA mode not enabled */
}
void St7735r::init() {
_pin_ss.init(GPIO_Mode_Out_PP, GPIO_Speed_50MHz);
_pin_reset.init(GPIO_Mode_Out_PP, GPIO_Speed_50MHz);
_pin_rs.init(GPIO_Mode_Out_PP, GPIO_Speed_50MHz);
_spi.init(SPI_Direction_2Lines_FullDuplex, SPI_Mode_Master, SPI_DataSize_8b,
SPI_CPOL_Low, SPI_CPHA_1Edge, SPI_NSS_Soft, SPI_BaudRatePrescaler_2,
SPI_FirstBit_MSB, 7);
SPI_I2S_DMACmd(_spi.base(), SPI_I2S_DMAReq_Tx, ENABLE);
_pin_ss.set(Bit_SET);
_pin_reset.set(Bit_SET);
delay(10);
_pin_reset.set(Bit_RESET);
delay(10);
_pin_reset.set(Bit_SET);
delay(10);
for (const instruction * cmd = initializers; cmd->command; cmd++) {
this->command(cmd->command);
if (cmd->len) write8(true, cmd->data, cmd->len);
if (cmd->delay) delay(cmd->delay);
}
_dma.setPeriphToConf((uint32_t) &(_spi.base()->DR),
DMA_PeripheralDataSize_HalfWord, DMA_PeripheralInc_Disable );
_dma.setFunctionToConf();
}
void setIRQandDMA(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
DMA_Cmd(DMA1_Stream7, DISABLE);
DMA_DeInit(DMA1_Stream7);
DMA_InitStructure.DMA_Channel = DMA_Channel_0;
DMA_InitStructure.DMA_PeripheralBaseAddr = 0x40003C0C;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA1_Stream7, &DMA_InitStructure);
DMA_ITConfig(DMA1_Stream7, DMA_IT_TC, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream7_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
SPI_I2S_DMACmd(SPI3, SPI_I2S_DMAReq_Tx, ENABLE);
}
void DMA1_Stream4_IRQHandler(void)
{
u16 i;
u8 tmp;
if(DMA_GetITStatus(DMA1_Stream4, DMA_IT_TCIF4) == SET)
{
TP3_L;
DMA_ClearITPendingBit(DMA1_Stream4, DMA_IT_TCIF4);
for(i=0;i<200;i++)
{
__nop();
}
DMA_Cmd(DMA1_Stream4,DISABLE);
SPI_I2S_DMACmd(SPIFLASH_SPI,SPI_I2S_DMAReq_Tx,DISABLE);
tmp=SPI_I2S_ReceiveData(SPIFLASH_SPI);
SPIFLASH_CS_H;
DMA_Tx_Busy = 0;
TP3_H;
}
else if(DMA_GetITStatus(DMA1_Stream4,DMA_IT_TEIF4) == SET)
{
__nop();
DMA_ClearITPendingBit(DMA1_Stream4, DMA_IT_TEIF4);
}
}
static void DMA_Configuration(rt_uint32_t addr, rt_size_t size)
{
DMA_InitTypeDef DMA_InitStructure;
/* DMA Channel configuration ----------------------------------------------*/
DMA_Cmd(CODEC_I2S_DMA, DISABLE);
DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(CODEC_I2S_PORT->DR));
DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = size;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(CODEC_I2S_DMA, &DMA_InitStructure);
/* Enable SPI DMA Tx request */
SPI_I2S_DMACmd(CODEC_I2S_PORT, SPI_I2S_DMAReq_Tx, ENABLE);
DMA_ITConfig(CODEC_I2S_DMA, DMA_IT_TC, ENABLE);
DMA_Cmd(CODEC_I2S_DMA, ENABLE);
}
void max7456_dma_irq_handler(dmaChannelDescriptor_t* descriptor) {
if (DMA_GET_FLAG_STATUS(descriptor, DMA_IT_TCIF)) {
#ifdef MAX7456_DMA_CHANNEL_RX
DMA_Cmd(MAX7456_DMA_CHANNEL_RX, DISABLE);
#else
//Empty RX buffer. RX DMA takes care of it if enabled
while (SPI_I2S_GetFlagStatus(MAX7456_SPI_INSTANCE, SPI_I2S_FLAG_RXNE) == SET) {
MAX7456_SPI_INSTANCE->DR;
}
#endif
DMA_Cmd(MAX7456_DMA_CHANNEL_TX, DISABLE);
DMA_CLEAR_FLAG(descriptor, DMA_IT_TCIF);
SPI_I2S_DMACmd(MAX7456_SPI_INSTANCE,
#ifdef MAX7456_DMA_CHANNEL_RX
SPI_I2S_DMAReq_Rx |
#endif
SPI_I2S_DMAReq_Tx, DISABLE);
DISABLE_MAX7456;
for (uint16_t x = 0; x < max_screen_size; x++)
max7456_screen[x + 3] = MAX7456_CHAR(' ');
dma_transaction_in_progress = 0;
}
}
/**
* @brief Initializes and prepares the Media to perform audio data transfer
* from Media to the I2S peripheral.
* @param None.
* @retval None.
*/
void Audio_MAL_Init(void)
{
#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
NVIC_InitTypeDef NVIC_InitStructure;
#endif
/* Enable the DMA clock */
RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE);
/* Configure the DMA Stream */
DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE);
DMA_DeInit(AUDIO_MAL_DMA_STREAM);
/* Set the parameters to be configured */
DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL;
DMA_InitStructure.DMA_PeripheralBaseAddr = CODEC_I2S_ADDRESS;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE;
DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE;
#ifdef AUDIO_MAL_MODE_NORMAL
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
#elif defined(AUDIO_MAL_MODE_CIRCULAR)
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
#else
#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!"
#endif /* AUDIO_MAL_MODE_NORMAL */
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure);
/* Enable the selected DMA interrupts (selected in "stm32_eval_audio_codec.h" defines) */
#ifdef AUDIO_MAL_DMA_IT_TC_EN
DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE);
#endif /* AUDIO_MAL_DMA_IT_TC_EN */
#ifdef AUDIO_MAL_DMA_IT_HT_EN
DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE);
#endif /* AUDIO_MAL_DMA_IT_HT_EN */
#ifdef AUDIO_MAL_DMA_IT_TE_EN
DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE);
#endif /* AUDIO_MAL_DMA_IT_TE_EN */
/* Enable the I2S DMA request */
SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE);
#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN)
/* I2S DMA IRQ Channel configuration */
NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
}
// Waits for DMA transfer to complete
static void oled_wait_dma(void) {
while(!DMA_GetFlagStatus(DMA2_Stream3, DMA_FLAG_TCIF3)) {
if(!DMA2_Stream3->NDTR) break;
}
DMA_ClearITPendingBit(DMA2_Stream3, DMA_IT_TCIF3);
DMA_Cmd(DMA2_Stream3, DISABLE);
SPI_I2S_DMACmd(OLED_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
}
static void HAL_SPI_TX_DMA_Stream_InterruptHandler(HAL_SPI_Interface spi)
{
if (DMA_GetITStatus(spiMap[spi].SPI_TX_DMA_Stream, spiMap[spi].SPI_TX_DMA_Stream_TC_Event) == SET)
{
DMA_ClearITPendingBit(spiMap[spi].SPI_TX_DMA_Stream, spiMap[spi].SPI_TX_DMA_Stream_TC_Event);
SPI_I2S_DMACmd(spiMap[spi].SPI_Peripheral, SPI_I2S_DMAReq_Tx, DISABLE);
DMA_Cmd(spiMap[spi].SPI_TX_DMA_Stream, DISABLE);
}
}
void TM_PCD8544_DeInitDMA(void) {
/* Disable DMA */
DMA_Cmd(PCD8544_DMA_STREAM, DISABLE);
/* Disable SPI transmit DMA */
SPI_I2S_DMACmd(PCD8544_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
/* CE high to stop transfer data */
PCD8544_CE_HIGH;
}
/**
* @brief I2S_Stop 停止iis总线
* @param none
* @retval none
*/
void I2S_Stop(void)
{
/* 禁能 SPI2/I2S2 外设 */
SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Tx, DISABLE);
I2S_Cmd(SPI2, DISABLE);
DMA_Cmd(DMA1_Channel5, DISABLE);
}
void SPIData_Init(void)
{
SPI_InitTypeDef SPI_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable clocks */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE );
RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA, ENABLE);
/* Use Alternate Functions for SPI pins */
GPIO_PinAFConfig( GPIOA, GPIO_PinSource5, GPIO_AF_SPI1 );
//L.GPIO_PinAFConfig( GPIOA, GPIO_PinSource6, GPIO_AF_SPI1 );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource7, GPIO_AF_SPI1 );
GPIO_PinAFConfig( GPIOA, GPIO_PinSource4, GPIO_AF_SPI1 );
/* Setup pin types */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN;
GPIO_InitStructure.GPIO_Pin = SPIDATA_CS_PIN;
GPIO_Init( GPIOA, &GPIO_InitStructure );
GPIO_InitStructure.GPIO_Pin = SPIDATA_SCK_PIN;
GPIO_Init( GPIOA, &GPIO_InitStructure );
GPIO_InitStructure.GPIO_Pin = SPIDATA_MOSI_PIN;
GPIO_Init( GPIOA, &GPIO_InitStructure );
SPI_I2S_DeInit(SPIDATA_PORT);
SPI_Cmd(SPIDATA_PORT, DISABLE);
SPI_StructInit(&SPI_InitStructure);
/*!< SPI configuration */
SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_RxOnly; /* 数据方向：2线只接收 */
SPI_InitStructure.SPI_Mode = SPI_Mode_Slave; /* STM32的SPI工作模式 ：从机模式 */
SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; /* 数据位长度 ： 8位 */
SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; /* 时钟下降沿采样数据 */
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; /* 时钟的第1个边沿采样数据 */
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;//SPI_NSS_Hard; //SPI_NSS_Soft; /* 片选控制方式：软件控制 */
//L.SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; /* 波特率预分频系数：4分频 */
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8;
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; /* 数据位传输次序：高位先传 */
SPI_InitStructure.SPI_CRCPolynomial = 7; /* CRC多项式寄存器，复位后为7。本例程不用 */
SPI_Init(SPIDATA_PORT, &SPI_InitStructure);
/* Enable the SPI peripheral */
SPI_I2S_DMACmd(SPIDATA_PORT,SPI_I2S_DMAReq_Rx,ENABLE);
SPI_Cmd(SPIDATA_PORT, ENABLE); /* enable SPI1 module */
SPIData_DMA_Init((u32)CodecRxBuffer);
}
void EF_spiFlashDmaTx(u8* buff,u16 length)
{
while(DMA_Tx_Busy == 1)
__nop();
DMA_Tx_Busy = 1;
DMA_Cmd(DMA1_Stream4,DISABLE);
DMA1_Stream4->M0AR = (u32)buff;
SPI_I2S_DMACmd(SPIFLASH_SPI,SPI_I2S_DMAReq_Tx,ENABLE);
DMA_Cmd(DMA1_Stream4,ENABLE);
}
void SPI_Config(void) {
GPIO_InitTypeDef structGPIO;
SPI_InitTypeDef structSPI;
DMA_InitTypeDef structDMA;
NVIC_InitTypeDef NVIC_InitStructure;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA1, ENABLE);
//configure GPIO
structGPIO.GPIO_Pin = GPIO_Pin_4;
structGPIO.GPIO_Mode = GPIO_Mode_AF;
structGPIO.GPIO_Speed = GPIO_Speed_50MHz;
structGPIO.GPIO_OType = GPIO_OType_PP;
structGPIO.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &structGPIO);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource4, GPIO_AF_SPI3);
structGPIO.GPIO_Pin =GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
GPIO_Init(GPIOC, &structGPIO);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_SPI3);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_SPI3);
GPIO_PinAFConfig(GPIOC, GPIO_PinSource12, GPIO_AF_SPI3);
//init spi
SPI_StructInit(&structSPI);
structSPI.SPI_Direction = SPI_Direction_1Line_Tx;
structSPI.SPI_Mode = SPI_Mode_Master;
structSPI.SPI_DataSize = SPI_DataSize_16b;
SPI_Init(SPI3, &structSPI);
//init DMA
SPI_I2S_DMACmd(SPI3, SPI_I2S_DMAReq_Tx, ENABLE);
structDMA.DMA_Channel = DMA_Channel_0;
structDMA.DMA_PeripheralBaseAddr = SPI3_ADDR;
structDMA.DMA_Memory0BaseAddr = (uint32_t)pb_spi->pbuf;
structDMA.DMA_DIR = DMA_DIR_MemoryToPeripheral;
structDMA.DMA_BufferSize = SIZE_BIG_BUFFER/2;
structDMA.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
structDMA.DMA_MemoryInc = DMA_MemoryInc_Enable;
structDMA.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
structDMA.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
structDMA.DMA_Mode = DMA_Mode_Normal;
structDMA.DMA_Priority = DMA_Priority_Medium;
structDMA.DMA_FIFOMode = DMA_FIFOMode_Disable;
structDMA.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
DMA_Init(DMA1_Stream5, &structDMA);
//init DMA interrupt
DMA_ITConfig(DMA1_Stream0, DMA_IT_TC, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = DMA1_Stream5_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 5;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
//enable DMA
DMA_Cmd(DMA1_Stream5, DISABLE);
//enable SPI
SPI_Cmd(SPI3, ENABLE);
}
uint8_t nRF24L01_WriteRegister(uint8_t cmd, uint8_t* pdata, uint8_t len)
{
uint8_t i, status;
uint8_t txbuf[33] = {0xFF};
for(i = 0; i < len; i++)
txbuf[i+1] = *(pdata+i);
txbuf[0] = cmd;
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Tx, ENABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Rx, ENABLE);
GPIO_ResetBits(NRF24L01_SPI_GPIO, NRF24L01_GPIO_CSN);
nRF24L01_Delay(5);
nRF24L01_TxDMAInit((uint8_t*)&txbuf, len+1);
nRF24L01_RxDMAInit(&status, 1);
DMA_Cmd(SPIx_TX_DMA_STREAM, ENABLE);
DMA_Cmd(SPIx_RX_DMA_STREAM, ENABLE);
while (DMA_GetFlagStatus(SPIx_TX_DMA_STREAM,SPIx_TX_DMA_TCIF)==RESET);
while (DMA_GetFlagStatus(SPIx_RX_DMA_STREAM,SPIx_RX_DMA_TCIF)==RESET);
/* Clear DMA Transfer Complete Flags */
DMA_ClearFlag(SPIx_TX_DMA_STREAM, SPIx_TX_DMA_TCIF);
DMA_ClearFlag(SPIx_RX_DMA_STREAM, SPIx_RX_DMA_TCIF);
DMA_Cmd(SPIx_RX_DMA_STREAM, DISABLE);
DMA_Cmd(SPIx_TX_DMA_STREAM, DISABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Rx, DISABLE);
nRF24L01_Delay(5);
GPIO_SetBits(NRF24L01_SPI_GPIO, NRF24L01_GPIO_CSN);
return status;
}
void SPIx_Tx_DMA_IRQHandler(void)
{
/* Test on Tx DMA Channel Transfer Complete interrupt */
if (DMA_GetITStatus(SPIx_Tx_DMA_Flag))
{
/* Clear DMA Channel Half Transfer, Transfer Complete and Global interrupt pending bits */
DMA_ClearITPendingBit(SPIx_Tx_DMA_CLR_Pendings);
DMA_ITConfig(SPIx_Tx_DMA_Channel, DMA_IT_TC, DISABLE);
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Tx, DISABLE);
DMA_Cmd(SPIx_Tx_DMA_Channel, DISABLE);
}
}
// Blocking SPI transfer
static void spi_transfer() {
// Enable NSS output for master mode
SPI_SSOutputCmd(SPI1, ENABLE);
// Enable DMA1 Channel1 Transfer Complete interrupt
//DMA_ITConfig(SPI1_TX_DMA_CHANNEL, DMA_IT_TC, ENABLE);
// Enable the DMA channels
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Rx, ENABLE);
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, ENABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL, ENABLE);
DMA_Cmd(SPI1_TX_DMA_CHANNEL, ENABLE);
// Wait for everything to finish
//TODO: Implement timeout so we don't get stuck
//uint32_t TimeOut = USER_TIMEOUT;
while ((DMA_GetFlagStatus(SPI1_RX_DMA_FLAG_TC) == RESET));
while ((DMA_GetFlagStatus(SPI1_TX_DMA_FLAG_TC) == RESET));
/* The BSY flag can be monitored to ensure that the SPI communication is complete.
This is required to avoid corrupting the last transmission before disabling
the SPI or entering the Stop mode. The software must first wait until TXE=1
and then until BSY=0.*/
while ((SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET));
while ((SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET));
// End the SPI transaction and DMA
// Clear DMA1 global flags
DMA_ClearFlag(SPI1_TX_DMA_FLAG_GL);
DMA_ClearFlag(SPI1_RX_DMA_FLAG_GL);
// Disable the DMA channels
DMA_Cmd(SPI1_RX_DMA_CHANNEL, DISABLE);
DMA_Cmd(SPI1_TX_DMA_CHANNEL, DISABLE);
// Disable the SPI Rx and Tx DMA requests
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Rx, DISABLE);
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, DISABLE);
}
