/**************************************************
Function: Receive_Packet
Description:
read FIFO to read a packet
Parameter:
None
Return:
None
**************************************************/
char Receive_Packet(char * buf, char buf_len)
{
UINT8 len,i,sta,fifo_sta,value,chksum,aa, res = 0;
UINT8 rx_buf[MAX_PACKET_LEN];
sta=SPI_Read_Reg(STATUS); // read register STATUS's value
if((STATUS_RX_DR&sta) == 0x40) // if receive data ready (RX_DR) interrupt
{
do
{
len=SPI_Read_Reg(R_RX_PL_WID_CMD); // read len
if(len<=MAX_PACKET_LEN)
{
SPI_Read_Buf(RD_RX_PLOAD,buf,len);// read receive payload from RX_FIFO buffer
}
else
{
SPI_Write_Reg(FLUSH_RX,0);//flush Rx
}
fifo_sta=SPI_Read_Reg(FIFO_STATUS); // read register FIFO_STATUS's value
}while((fifo_sta&FIFO_STATUS_RX_EMPTY)==0); //while not empty
/*
chksum = 0;
for(i=0;i<16;i++)
{
chksum +=rx_buf[i];
}
if(chksum==rx_buf[16]&&rx_buf[0]==0x30)
{
// GREEN_LED = 1;
// delay_50ms();
// delay_50ms();
// GREEN_LED = 0;
_delay_ms(100);
//Send_Packet(W_TX_PAYLOAD_NOACK_CMD,rx_buf,17);
SwitchToRxMode();//switch to RX mode
res = 1;
}
*/
res = len;
}
SPI_Write_Reg(WRITE_REG|STATUS,sta);// clear RX_DR or TX_DS or MAX_RT interrupt flag
return res;
}
void SwitchToRxMode()
{
UINT8 value;
SPI_Write_Reg(FLUSH_RX,0);//flush Rx
value=SPI_Read_Reg(STATUS); // read register STATUS's value
SPI_Write_Reg(WRITE_REG|STATUS,value);// clear RX_DR or TX_DS or MAX_RT interrupt flag
DOWNBIT(SPIPORT,CE);//CE=0;
value=SPI_Read_Reg(CONFIG); // read register CONFIG's value
//PRX
value=value|0x01;//set bit 1
SPI_Write_Reg(WRITE_REG | CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled..
UPBIT(SPIPORT,CE);//CE=1;
}
void SwitchCFG(char _cfg)//1:Bank1 0:Bank0
{
UINT8 Tmp;
Tmp=SPI_Read_Reg(7);
Tmp=Tmp&0x80;
if( ( (Tmp)&&(_cfg==0) )
||( ((Tmp)==0)&&(_cfg) ) )
{
SPI_Write_Reg(ACTIVATE_CMD,0x53);
}
}
void SwitchToTxMode()
{
UINT8 value;
SPI_Write_Reg(FLUSH_TX,0);//flush Tx
DOWNBIT(SPIPORT,CE);//CE=0;
value=SPI_Read_Reg(CONFIG); // read register CONFIG's value
//PTX
value=value&0xfe;//set bit 0
SPI_Write_Reg(WRITE_REG | CONFIG, value); // Set PWR_UP bit, enable CRC(2 length) & Prim:RX. RX_DR enabled.
UPBIT(SPIPORT,CE);//CE=1;
}
uchar NRF24L01_RxPacket(uchar *rxbuf)
{
uchar stat = 0;
stat = SPI_Read_Reg(STATUS);
SPI_Write_Reg(WRITE_REG + STATUS, stat);
if(stat&RX_OK)
{
NRF_CE0;
SPI_Read_Buf(RD_RX_PLOAD,rxbuf,RX_PLOAD_WIDTH);
SPI_Write_Reg(FLUSH_RX,0xff);
NRF_CE1;
Delay_us(130); ///???
return 1;
}
return 0;
}
uchar NRF24L01_TxPacket(uchar *txbuf)
{
uchar stat = 0;
NRF_CE0;
SPI_Write_Buf(WR_TX_PLOAD,txbuf,TX_PLOAD_WIDTH);
NRF_CE1;
while(NRF_IRQ_READ);
stat = SPI_Read_Reg(STATUS);
SPI_Write_Reg(WRITE_REG+STATUS,stat);
if(stat&MAX_TX)//达到最大重发次数
{
SPI_Write_Reg(FLUSH_TX,0xff);//清除TX FIFO寄存器
return MAX_TX;
}
if(stat&TX_OK)//发送完成
{
return TX_OK;
}
return 0xff;//发送失败
}
/**************************************************
Function: Send_Packet
Description:
fill FIFO to send a packet
Parameter:
type: WR_TX_PLOAD or W_TX_PAYLOAD_NOACK_CMD
pbuf: a buffer pointer
len: packet length
Return:
None
**************************************************/
char Send_Packet(UINT8 type,UINT8* pbuf,UINT8 len)
{
UINT8 fifo_sta;
SwitchToTxMode(); //switch to tx mode
fifo_sta=SPI_Read_Reg(FIFO_STATUS); // read register FIFO_STATUS's value
if((fifo_sta&FIFO_STATUS_TX_FULL)==0)//if not full, send data (write buff)
{
//RED_LED = 1;
SPI_Write_Buf(type, pbuf, len); // Writes data to buffer
//delay_50ms();
//RED_LED = 0;
//delay_50ms();
_delay_ms(100);
}
return 0;
}
void RFM73_Initialize()
{
UINT8 i,j,temp;
UINT8 WriteArr[12];
//DelayMs(100);//delay more than 50ms.
_delay_ms(200);
SwitchCFG(0);
for(i=0;i<20;i++)
{
SPI_Write_Reg((WRITE_REG|Bank0_Reg[i][0]),Bank0_Reg[i][1]);
}
/*//reg 10 - Rx0 addr
SPI_Write_Buf((WRITE_REG|10),RX0_Address,5);
//REG 11 - Rx1 addr
SPI_Write_Buf((WRITE_REG|11),RX1_Address,5);
//REG 16 - TX addr
SPI_Write_Buf((WRITE_REG|16),RX0_Address,5);*/
//reg 10 - Rx0 addr
for(j=0;j<5;j++)
{
WriteArr[j]=RX0_Address[j];
}
SPI_Write_Buf((WRITE_REG|10),&(WriteArr[0]),5);
//REG 11 - Rx1 addr
for(j=0;j<5;j++)
{
WriteArr[j]=RX1_Address[j];
}
SPI_Write_Buf((WRITE_REG|11),&(WriteArr[0]),5);
//REG 16 - TX addr
for(j=0;j<5;j++)
{
WriteArr[j]=RX0_Address[j];
}
SPI_Write_Buf((WRITE_REG|16),&(WriteArr[0]),5);
// printf("\nEnd Load Reg");
i=SPI_Read_Reg(29);//read Feature Register ???????§??¶??¬?¤¶?»??? Payload With ACK?¬???????????¬·??? ACTIVATE????????????0x73),?»??????¶??¬?¤¶?»??? Payload With ACK (REG28,REG29).
if(i==0) // i!=0 showed that chip has been actived.so do not active again.
SPI_Write_Reg(ACTIVATE_CMD,0x73);// Active
for(i=22;i>=21;i--)
{
SPI_Write_Reg((WRITE_REG|Bank0_Reg[i][0]),Bank0_Reg[i][1]);
//SPI_Write_Reg_Bank0(Bank0_Reg[i][0],Bank0_Reg[i][1]);
}
//********************Write Bank1 register******************
SwitchCFG(1);
for(i=0;i<=8;i++)//reverse
{
for(j=0;j<4;j++)
WriteArr[j]=(Bank1_Reg0_13[i]>>(8*(j) ) )&0xff;
SPI_Write_Buf((WRITE_REG|i),&(WriteArr[0]),4);
}
for(i=9;i<=13;i++)
{
for(j=0;j<4;j++)
WriteArr[j]=(Bank1_Reg0_13[i]>>(8*(3-j) ) )&0xff;
SPI_Write_Buf((WRITE_REG|i),&(WriteArr[0]),4);
}
//SPI_Write_Buf((WRITE_REG|14),&(Bank1_Reg14[0]),11);
for(j=0;j<11;j++)
{
WriteArr[j]=Bank1_Reg14[j];
}
SPI_Write_Buf((WRITE_REG|14),&(WriteArr[0]),11);
//toggle REG4<25,26>
for(j=0;j<4;j++)
//WriteArr[j]=(RegArrFSKAnalog[4]>>(8*(j) ) )&0xff;
WriteArr[j]=(Bank1_Reg0_13[4]>>(8*(j) ) )&0xff;
WriteArr[0]=WriteArr[0]|0x06;
SPI_Write_Buf((WRITE_REG|4),&(WriteArr[0]),4);
WriteArr[0]=WriteArr[0]&0xf9;
SPI_Write_Buf((WRITE_REG|4),&(WriteArr[0]),4);
//**************************Test spi*****************************//
//SPI_Write_Reg((WRITE_REG|Bank0_Reg[2][0]),0x0f);
//test_data = SPI_Read_Reg(0x02);
//DelayMs(10);
_delay_ms(50);
//********************switch back to Bank0 register access******************
SwitchCFG(0);
SwitchToRxMode();//switch to RX mode
}
