void Peggy2::RefreshAll(unsigned int refreshNum)
{
unsigned int i,k;
unsigned char j;
union mix_t {
unsigned long atemp;
unsigned char c[4];
} mix;
k = 0;
while (k != refreshNum)
{
k++;
j = 0;
while (j < 25)
{
if (j == 0)
PORTD = 160;
else if (j < 16)
PORTD = j;
else
PORTD = (j - 15) << 4;
i = 0;
while (i < 50)
{
asm("nop");
i++;
}
mix.atemp = buffer[j];
SPI_TX(mix.c[3]);
SPI_TX(mix.c[2]);
SPI_TX(mix.c[1]);
PORTD = 0; // Turn displays off
SPI_TX(mix.c[0]);
PORTB |= 2U; //Latch Pulse
PORTB &= 253U;
j++;
}
}
}
//----------------------------Interrupt Routine---------------------------------
//USART1 Receive complete interrupt service routine
//clear RXCn bit by reading receiver buffer, UDR1
//send data using SPI to digital phase shifter here
ISR(USART1_RX_vect, ISR_BLOCK){
++usart_byte_count; //expect to receive 4 commands
uint8_t RX_byte = UDR1; //read data from USART1 buffer
if(usart_byte_count == 1){
if(RX_byte == 0xFF){ //cmd sync
cmd_start = true;
} else { //reset count if no start of cmd detected
usart_byte_count = 0;
}
} else if(cmd_start){
if(usart_byte_count == 2){ // second byte contains address
if(RX_byte != DPS_addr){ //if address does not match
usart_byte_count = 0; //restart
cmd_start = false;
}
} else if(usart_byte_count == 3){ //port number
port_num = RX_byte; //read port number
} else if(usart_byte_count == 4){ //phase shift
//read data from USART buffer 1 then send to DPS chip
SPI_TX(port_num, RX_byte, bit_sh);
usart_byte_count = 0;
cmd_start = false;
} //end of else if
} //end of else if
} //end of ISR
inline
void
spiWrite8(
long address,
char data
)
{
char i, command = 2;
CS = 0;
address <<= 8;
SPI_TX(i, 8, command);
SPI_TX(i, 24, address);
SPI_TX(i, 8, data);
CS = 1;
delay_us(100);
}
void hal_spi_write_byte( uint8 data)
{
SPI_BEGIN();
SPI_TX(data);
SPI_WAIT_TXRDY();
SPI_END();
}
inline
void
spiWriteEnable(
)
{
char i, command = 6; //write enable
CS = 0;
SPI_TX(i, 8, command);
CS = 1;
}
inline
void
spiChipErase(
)
{
char i, command = 0x62;
CS = 0;
SPI_TX(i, 8, command);
CS = 1;
delay_ms(5000);
}
inline
void
spiWriteBlock(
long address,
char *pBlock,
char blockSize
)
{
char i, b, command = 2, dt;
CS = 0;
address <<= 8;
SPI_TX(i, 8, command);
SPI_TX(i, 24, address);
for (b = 0; b < blockSize; ++b) {
dt = *(pBlock + b);
SPI_TX(i, 8, dt);
}
CS = 1;
delay_us(100);
}
//===========================================================================//
// чете Status Reg на Flash чипа
uint8_t AT45DB_ReadStatusReg( void )
{
// char res;
// set_spi(2, 0);
// spi_io(0xFF); spi_io(0xFF);
// select_flash(); // CS > Low ( active )
// spi_io(0x57); // 'read_status_reg' cmd
// res = spi_io(0xFF);
// deselect_flash(); // CS > High ( inactive )
// return res;
uint8_t u8ResultL;
select_flash();
u8ResultL = SPI_TX( 0xd7 );
u8ResultL = SPI_TX( 0x00 );
deselect_flash();
return u8ResultL;
}
inline
char
spiRead8(
long address
)
{
char i, command = 3, result = 0;
CS = 0;
address <<= 8;
SPI_TX(i, 8, command);
SPI_TX(i, 24, address);
for (i = 0; i < 8; ++i) {
SCK = 1;
result <<= 1;
if (SI)
++result;
SCK = 0;
}
CS = 1;
return result;
}
void Peggy2::HardwareInit()
{
// Hardware Initialization:
PORTD = 0U;
DDRD = 255U;
////SET MOSI, SCK Output, all other SPI as input:
DDRB |= _BV(5) | _BV(3) | _BV(2) | _BV(1);
//ENABLE SPI, MASTER, CLOCK RATE fck/4:
SPCR = _BV(SPE) | _BV(MSTR) ;
// Flush SPI LED drivers::
SPI_TX(0);
SPI_TX(0);
SPI_TX(0);
SPI_TX(0);
PORTB |= 2; //Latch Pulse
PORTB &= 253;
}
inline
char
spiReadStatus(
)
{
char i, res = 5;
CS = 0;
SPI_TX(i, 8, res);
for (i = 0; i < 8; ++i) {
SCK = 1;
res <<= 1;
if (SI)
++res;
SCK = 0;
}
CS = 1;
return res;
}
