int SSD_PAGE_WRITE(unsigned int flash_nb, unsigned int block_nb, unsigned int page_nb, int offset, int type, int io_page_nb)
{
int channel, reg;
int ret = FAIL;
int delay_ret;
/* Calculate ch & reg */
channel = flash_nb % CHANNEL_NB;
reg = flash_nb*PLANES_PER_FLASH + block_nb%PLANES_PER_FLASH;
/* Delay Operation */
SSD_CH_ENABLE(channel); // channel enable
if( IO_PARALLELISM == 0 ){
delay_ret = SSD_FLASH_ACCESS(flash_nb, reg);
}
else{
delay_ret = SSD_REG_ACCESS(reg);
}
/* Check Channel Operation */
while(ret == FAIL){
ret = SSD_CH_ACCESS(channel);
}
/* Record Time Stamp */
SSD_CH_RECORD(channel, WRITE, offset, delay_ret);
SSD_REG_RECORD(reg, WRITE, type, offset, channel);
SSD_CELL_RECORD(reg, WRITE);
#ifdef O_DIRECT_VSSIM
if(offset == io_page_nb-1){
SSD_REMAIN_IO_DELAY(reg);
}
#endif
// printf("WRITE reg %d\tch %d\toff %d\n", reg, channel, offset);
// SSD_PRINT_STAMP();
return SUCCESS;
}
int SSD_BLOCK_ERASE(unsigned int flash_nb, unsigned int block_nb)
{
int channel, reg;
/* Calculate ch & reg */
channel = flash_nb % CHANNEL_NB;
reg = flash_nb*PLANES_PER_FLASH + block_nb%PLANES_PER_FLASH;
/* Delay Operation */
if( IO_PARALLELISM == 0 ){
SSD_FLASH_ACCESS(flash_nb, reg);
}
else{
SSD_REG_ACCESS(reg);
}
/* Record Time Stamp */
SSD_REG_RECORD(reg, ERASE, ERASE, -1, channel);
SSD_CELL_RECORD(reg, ERASE);
return SUCCESS;
}
int SSD_PAGE_PARTIAL_WRITE(unsigned int old_flash_nb, unsigned int old_block_nb, unsigned int old_page_nb, unsigned int new_flash_nb, unsigned int new_block_nb, unsigned int new_page_nb, int offset, int type, int io_page_nb)
{
int channel, reg;
int ret = FAIL;
int delay_ret;
/* READ Partial Data */
/* Calculate ch & reg */
channel = old_flash_nb % CHANNEL_NB;
reg = old_flash_nb*PLANES_PER_FLASH + old_block_nb%PLANES_PER_FLASH;
/* Delay Operation */
SSD_CH_ENABLE(channel); // channel enable
if( IO_PARALLELISM == 0 ){
delay_ret = SSD_FLASH_ACCESS(old_flash_nb, reg);
}
else{
delay_ret = SSD_REG_ACCESS(reg);
}
/* Check Channel Operation */
while(ret == FAIL){
ret = SSD_CH_ACCESS(channel);
}
/* Record Time Stamp */
SSD_CH_RECORD(channel, READ, offset, delay_ret);
SSD_REG_RECORD(reg, READ, type, offset, channel);
SSD_CELL_RECORD(reg, READ);
SSD_REMAIN_IO_DELAY(reg);
/* Write 1 Page */
/* Calculate ch & reg */
channel = new_flash_nb % CHANNEL_NB;
reg = new_flash_nb*PLANES_PER_FLASH + new_block_nb%PLANES_PER_FLASH;
/* Delay Operation */
SSD_CH_ENABLE(channel); // channel enable
if( IO_PARALLELISM == 0 ){
delay_ret = SSD_FLASH_ACCESS(new_flash_nb, reg);
}
else{
delay_ret = SSD_REG_ACCESS(reg);
}
/* Check Channel Operation */
while(ret == FAIL){
ret = SSD_CH_ACCESS(channel);
}
/* Record Time Stamp */
SSD_CH_RECORD(channel, WRITE, offset, delay_ret);
SSD_REG_RECORD(reg, WRITE, type, offset, channel);
SSD_CELL_RECORD(reg, WRITE);
#ifdef O_DIRECT_VSSIM
if(offset == io_page_nb-1){
SSD_REMAIN_IO_DELAY(reg);
}
#endif
return SUCCESS;
}
