//*****************************************************************************
//
//! Initializes the connection to the PDC.
//!
//! This function will enable clocking to the SSI and GPIO A modules, configure
//! the GPIO pins to be used for an SSI interface, and it will configure the
//! SSI as a 1 Mbps master device, operating in MOTO mode. It will also enable
//! the SSI module, and will enable the chip select for the PDC on the
//! Stellaris development board.
//!
//! This function is contained in <tt>utils/pdc.c</tt>, with
//! <tt>utils/pdc.h</tt> containing the API definition for use by applications.
//!
//! \return None.
//
//*****************************************************************************
void
PDCInit(void)
{
//
// Enable the peripherals used to drive the PDC.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
//
// Configure the appropriate pins to be SSI instead of GPIO.
//
GPIODirModeSet(GPIO_PORTA_BASE, SSI_CLK | SSI_TX | SSI_RX,
GPIO_DIR_MODE_HW);
GPIODirModeSet(GPIO_PORTA_BASE, SSI_CS, GPIO_DIR_MODE_OUT);
GPIOPadConfigSet(GPIO_PORTA_BASE, SSI_CLK, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Configure the SSI port.
//
SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
SSIEnable(SSI_BASE);
//
// Reset the PDC SSI state machine. The chip select needs to be held low
// for 100ns; the procedure call overhead more than accounts for this time.
//
GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, 0);
GPIOPinWrite(GPIO_PORTA_BASE, PDC_CS, PDC_CS);
}
void spi_init (void) {
/* Initialize and enable the SSP Interface module. */
/* Enable the SSI peripherals. */
SysCtlPeripheralEnable(SSIx_PERI);
SysCtlPeripheralEnable(SSI_PORT_PERI);
SysCtlPeripheralEnable(SD_CS_PORT_PERI);
SysCtlPeripheralEnable(CS_PORT_PERI);
/* Configure the appropriate pins to be SSI instead of GPIO */
GPIODirModeSet(SSI_PORT, SSI_PINS, GPIO_DIR_MODE_HW);
GPIODirModeSet(SD_CS_PORT, SD_SSI_CS, GPIO_DIR_MODE_OUT);
GPIODirModeSet(CS_PORT, SSI_CS, GPIO_DIR_MODE_OUT);
GPIOPadConfigSet(SSI_PORT, SSI_PINS, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
GPIOPadConfigSet(SD_CS_PORT, SD_SSI_CS, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
GPIOPadConfigSet(CS_PORT, SSI_CS, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
/* Deassert the SSIx chip select */
GPIOPinWrite(SD_CS_PORT, SD_SSI_CS, SD_SSI_CS);
GPIOPinWrite(CS_PORT, SSI_CS, SSI_CS);
/* Configure the SSIx port */
SSIConfig(SSIx_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 400000, 8);
//SSIConfig(SSIx_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 400000, 8);
//SSIConfig(SSIx_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 200000, 8);
SSIEnable(SSIx_BASE);
}
void spi_hi_speed (BOOL on) {
/* Set a SPI clock to low/high speed for SD/MMC. */
U32 clk;
if (on == __TRUE) {
/* Max. 20 MBit used for Data Transfer. */
clk = 12500000; /* Maximum allowed clock is 12.5MHz. */
}
else {
/* Max. 400 kBit used in Card Initialization. */
clk = 400000;
}
SSIDisable(SSIx_BASE);
SSIConfig (SSIx_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, clk, 8);
SSIEnable (SSIx_BASE);
}
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! \param ulFrequency specifies the SSI Clock Frequency to be used.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! This function is contained in <tt>rit128x96x4.c</tt>, with
//! <tt>rit128x96x4.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Enable(unsigned long ulFrequency)
{
unsigned long ulTemp;
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Configure the SSI0 port for master mode.
//
SSIConfig(SSI0_BASE, SSI_FRF_MOTO_MODE_2, SSI_MODE_MASTER, ulFrequency, 8);
//
// (Re)Enable SSI control of the FSS pin.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Enable the SSI port.
//
SSIEnable(SSI0_BASE);
//
// Drain the receive fifo.
//
while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)
{
}
//
// Indicate that the RIT driver can use the SSI Port.
//
g_bSSIEnabled = true;
}
