/* ------------------------------------------------------------------------------------------------------
* ssi0_Init()
*
* Description : SPI sysctl init function.
*
* Argument(s) : none.
*
*/
void BSP_SSI0_Init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SSIDisable(SSI0_BASE); /* Disable SSI0.*/
GPIOPinTypeSSI(GPIO_PORTA_BASE, /* Configure the SPI port*/
GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE,
GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5,
GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); /* Configure the CS port*/
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_STRENGTH_4MA,
GPIO_PIN_TYPE_STD_WPU);
SELECT();
DESELECT(); /* Deassert the SSI0 chip select */
SSIConfigSetExpClk(SSI0_BASE, /* Configure the SSI0 port */
SysCtlClockGet(),
SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 400000, 8);
SSIEnable(SSI0_BASE); /* Enable SSI0.*/
}
void Zone_Init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
GPIOPinTypeSSI(GPIO_PORTA_BASE,
GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5);
GPIOPadConfigSet(GPIO_PORTA_BASE,
GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIDisable(SSI0_BASE);
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 2000000, 8);
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3,
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIEnable(SSI0_BASE);
while(SSIBusy(SSI0_BASE)) {}
SSIDataPut(SSI0_BASE, ZONE_NONE);
}
/*
* ======== SPICC26XXDMA_hwInit ========
* This functions initializes the SPI hardware module.
*
* @pre Function assumes that the SPI handle is pointing to a hardware
* module which has already been opened.
*/
static void SPICC26XXDMA_initHw(SPI_Handle handle) {
SPICC26XX_Object *object;
SPICC26XX_HWAttrs const *hwAttrs;
Types_FreqHz freq;
/* Get the pointer to the object and hwAttrs */
object = handle->object;
hwAttrs = handle->hwAttrs;
/* Disable SSI operation */
SSIDisable(hwAttrs->baseAddr);
/* Disable SPI module interrupts */
SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF);
SSIIntClear(hwAttrs->baseAddr, SSI_RXOR | SSI_RXTO);
/* Set the SPI configuration */
BIOS_getCpuFreq(&freq);
SSIConfigSetExpClk(hwAttrs->baseAddr, freq.lo, frameFormat[object->frameFormat],
mode[object->mode], object->bitRate, object->dataSize);
/* Print the configuration */
Log_print3(Diags_USER1, "SPI:(%p) CPU freq: %d; SPI freq to %d",
hwAttrs->baseAddr, freq.lo, object->bitRate);
}
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Disable(void)
{
unsigned long ulTemp;
//
// Indicate that the RIT driver can no longer use the SSI Port.
//
HWREGBITW(&g_ulSSIFlags, FLAG_SSI_ENABLED) = 0;
//
// Drain the receive fifo.
//
while(SSIDataGetNonBlocking(SSI0_BASE, &ulTemp) != 0)
{
}
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Disable SSI control of the FSS pin.
//
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);
}
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! This function is contained in <tt>rit128x96x4.c</tt>, with
//! <tt>rit128x96x4.h</tt> containing the API definition for use by
//! applications.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Disable(void)
{
unsigned long ulTemp;
//
// Indicate that the RIT driver can no longer use the SSI Port.
//
g_bSSIEnabled = false;
//
// Drain the receive fifo.
//
while(SSIDataNonBlockingGet(SSI0_BASE, &ulTemp) != 0)
{
}
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Disable SSI control of the FSS pin.
//
GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);
}
/*#####################################################*/
void _mcspi_close(new_mcspi *McspiStruct)
{
SSIDisable(McspiStruct->BaseAddr);
switch(McspiStruct->McspiNr)
{
case 0:
IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->SckPin);
IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin);
IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MosiPin);
IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->CsPin[0]);
SSIConfigSetExpClk(SSI0_BASE, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize);
McspiStruct->BaseAddr = 0;
break;
case 1:
IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->SckPin);
IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin);
IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MosiPin);
IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->CsPin[0]);
SSIConfigSetExpClk(SSI1_BASE, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize);
McspiStruct->BaseAddr = 0;
break;
}
}
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! \param ulFrequency specifies the SSI Clock Frequency to be used.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Enable(unsigned long ulFrequency)
{
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Configure the SSI0 port for master mode.
//
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3,
SSI_MODE_MASTER, ulFrequency, 8);
//
// (Re)Enable SSI control of the FSS pin.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Enable the SSI port.
//
SSIEnable(SSI0_BASE);
//
// Indicate that the RIT driver can use the SSI Port.
//
HWREGBITW(&g_ulSSIFlags, FLAG_SSI_ENABLED) = 1;
}
/*#####################################################*/
bool _mcspi_set_baud(Mcspi_t *McspiStruct, unsigned long baud)
{
SSIDisable(McspiStruct->BaseAddr);
SSIConfigSetExpClk(McspiStruct->BaseAddr, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, baud, McspiStruct->WordSize);
SSIEnable(McspiStruct->BaseAddr);
McspiStruct->ClkDiv[McspiStruct->McspiNr] = baud;
return true;
}
static void sd_card_setspeed(int speed)
{
SSIDisable(SD_BASE_SSI);
SSIConfigSetExpClk(
SD_BASE_SSI, SysCtlClockGet(),
SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER,
speed, 8
);
SSIEnable(SD_BASE_SSI);
}
/**
Initializes the Serial Peripheral Interface (SPI) interface to the Zigbee Module (ZM).
@note Maximum module SPI clock speed is 4MHz. SPI port configured for clock polarity of 0, clock phase of 0, and MSB first.
@note On the GW the Stellaris uses SSI0 to communicate with module
@pre SPI pins configured correctly:
- Clock, MOSI, MISO configured as SPI function
- Chip Select configured as an output
- SRDY configured as an input.
@post SPI port is configured for communications with the module.
*/
void halSpiInitModule()
{
SSIDisable(SSI0_BASE);
// Reconfigure the SSI Port for Module operation.
// Clock polarity = inactive is LOW (CPOL=0); Clock Phase = 0; MSB first; Master Mode, 2mHz, data is 8bits wide;
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8);
// Enable the SSI Port.
SSIEnable(SSI0_BASE);
// Hold the module in reset
SPI_SS_CLEAR();
}
bool _mcspi_open(new_mcspi *McspiStruct)
{
switch(McspiStruct->McspiNr)
{
case 0:
SSIDisable(SSI0_BASE);
IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_MCU_SSI0_CLK, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->SckPin);
IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_MCU_SSI0_RX, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_ENABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin);
IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_MCU_SSI0_TX, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->MosiPin);
IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_MCU_SSI0_FSS, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->CsPin[0]);
SSIConfigSetExpClk(SSI0_BASE, CoreFreq, SSI_FRF_MOTO_MODE_3, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize);
McspiStruct->BaseAddr = SSI0_BASE;
break;
case 1:
SSIDisable(SSI1_BASE);
IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_MCU_SSI1_CLK, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->SckPin);
IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_MCU_SSI1_RX, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_ENABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin);
IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_MCU_SSI1_TX, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->MosiPin);
IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_MCU_SSI1_FSS, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE);
HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->CsPin[0]);
SSIConfigSetExpClk(SSI1_BASE, CoreFreq, SSI_FRF_MOTO_MODE_3, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize);
McspiStruct->BaseAddr = SSI1_BASE;
break;
default:
return false;
}
SSIEnable(McspiStruct->BaseAddr);
return true;//spi_enable(McspiStruct);
}
void spi_hi_speed (BOOL on) {
/* Set a SPI clock to low/high speed for SD/MMC. */
U32 clk;
if (on == __TRUE) {
/* Max. 20 MBit used for Data Transfer. */
clk = 12500000; /* Maximum allowed clock is 12.5MHz. */
}
else {
/* Max. 400 kBit used in Card Initialization. */
clk = 400000;
}
SSIDisable(SSIx_BASE);
SSIConfig (SSIx_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, clk, 8);
SSIEnable (SSIx_BASE);
}
void Spi::sleep(void)
{
SSIDisable(base_);
// Configure the MISO, MOSI, CLK and nCS pins as output
GPIOPinTypeGPIOOutput(miso_.getPort(), miso_.getPin());
GPIOPinTypeGPIOOutput(mosi_.getPort(), mosi_.getPin());
GPIOPinTypeGPIOOutput(clk_.getPort(), clk_.getPin());
// GPIOPinTypeGPIOOutput(ncs_.getPort(), ncs_.getPin());
//
GPIOPinWrite(miso_.getPort(), miso_.getPin(), 0);
GPIOPinWrite(mosi_.getPort(), mosi_.getPin(), 0);
GPIOPinWrite(clk_.getPort(), clk_.getPin(), 0);
// GPIOPinWrite(ncs_.getPort(), ncs_.getPin(), 0);
}
//*****************************************************************************
//
// Enable the SSI Port for FatFs usage.
//
//*****************************************************************************
void fs_enable(unsigned long ulFrequency)
{
//
// Disable the SSI Port.
//
SSIDisable(SSI0_BASE);
//
// Reconfigure the SSI Port for Fat FS operation.
//
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, ulFrequency, 8);
//
// Eanble the SSI Port.
//
SSIEnable(SSI0_BASE);
}
/*!
* @brief Function to close a given CC26XX SPI peripheral specified by the
* SPI handle.
*
* Will disable the SPI, disable all SPI interrupts and release the
* dependency on the corresponding power domain.
*
* @pre SPICC26XXDMA_open() has to be called first.
* Calling context: Task
*
* @param handle A SPI_Handle returned from SPI_open()
*
* @sa SPICC26XXDMA_open
*/
void SPICC26XXDMA_close(SPI_Handle handle)
{
unsigned int key;
SPICC26XX_Object *object;
SPICC26XX_HWAttrs const *hwAttrs;
/* Get the pointer to the object and hwAttrs */
hwAttrs = handle->hwAttrs;
object = handle->object;
/* Release the uDMA dependency and potentially power down uDMA. */
UDMACC26XX_close(object->udmaHandle);
/* Deallocate pins */
PIN_close(object->pinHandle);
/* Disable the SPI */
SSIDisable(hwAttrs->baseAddr);
/* Destroy the Hwi */
Hwi_destruct(&(object->hwi));
/* Release power dependency on SPI. */
Power_releaseDependency(hwAttrs->powerMngrId);
if (object->transferMode == SPI_MODE_BLOCKING) {
Semaphore_destruct(&(object->transferComplete));
}
/* Unregister power notification objects */
#ifdef SPICC26XXDMA_WAKEUP_ENABLED
Power_unregisterNotify(&object->spiPreObj);
#endif
Power_unregisterNotify(&object->spiPostObj);
/* Mark the module as available */
key = Hwi_disable();
object->isOpen = false;
Hwi_restore(key);
Log_print1(Diags_USER1, "SPI:(%p) closed", hwAttrs->baseAddr);
}
void Spi::enable(uint32_t baudrate)
{
GpioConfig& miso = miso_.getGpioConfig();
GpioConfig& mosi = mosi_.getGpioConfig();
GpioConfig& clk = clk_.getGpioConfig();
// GpioConfig& ncs = ncs_.getGpioConfig();
// Store baudrate in configuration
if (baudrate != 0) {
config_.baudrate = baudrate;
}
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(config_.peripheral);
SysCtrlPeripheralSleepEnable(config_.peripheral);
SysCtrlPeripheralDeepSleepDisable(config_.peripheral);
// Reset peripheral previous to configuring it
SSIDisable(config_.base);
// Set IO clock as SPI0 clock source
SSIClockSourceSet(config_.base, config_.clock);
// Configure the MISO, MOSI, CLK and nCS pins as peripheral
IOCPinConfigPeriphInput(miso.port, miso.pin, miso.ioc);
IOCPinConfigPeriphOutput(mosi.port, mosi.pin, mosi.ioc);
IOCPinConfigPeriphOutput(clk.port, clk.pin, clk.ioc);
// IOCPinConfigPeriphOutput(ncs.port, ncs.pin, ncs.ioc);
// Configure MISO, MOSI, CLK and nCS GPIOs
GPIOPinTypeSSI(miso.port, miso.pin);
GPIOPinTypeSSI(mosi.port, mosi.pin);
GPIOPinTypeSSI(clk.port, clk.pin);
// GPIOPinTypeSSI(ncs.port, ncs.pin);
// Configure the SPI0 clock
SSIConfigSetExpClk(config_.base, SysCtrlIOClockGet(), config_.protocol, \
config_.mode, config_.baudrate, config_.datawidth);
// Enable the SPI0 module
SSIEnable(config_.base);
}
u32 platform_spi_setup( unsigned id, int mode, u32 clock, unsigned cpol, unsigned cpha, unsigned databits )
{
unsigned protocol;
if( cpol == 0 )
protocol = cpha ? SSI_FRF_MOTO_MODE_1 : SSI_FRF_MOTO_MODE_0;
else
protocol = cpha ? SSI_FRF_MOTO_MODE_3 : SSI_FRF_MOTO_MODE_2;
mode = mode == PLATFORM_SPI_MASTER ? SSI_MODE_MASTER : SSI_MODE_SLAVE;
SSIDisable( spi_base[ id ] );
GPIOPinTypeSSI( spi_gpio_base[ id ], spi_gpio_pins[ id ] );
// FIXME: not sure this is always "right"
// GPIOPadConfigSet(spi_gpio_base[ id ], spi_gpio_clk_pin[ id ], GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
SSIConfigSetExpClk( spi_base[ id ], SysCtlClockGet(), protocol, mode, clock, databits );
SSIEnable( spi_base[ id ] );
return clock;
}
void Spi::sleep(void)
{
GpioConfig& miso = miso_.getGpioConfig();
GpioConfig& mosi = mosi_.getGpioConfig();
GpioConfig& clk = clk_.getGpioConfig();
// GpioConfig& ncs = ncs_.getGpioConfig();
SSIDisable(config_.base);
// Configure the MISO, MOSI, CLK and nCS pins as output
GPIOPinTypeGPIOOutput(miso.port, miso.pin);
GPIOPinTypeGPIOOutput(mosi.port, mosi.pin);
GPIOPinTypeGPIOOutput(clk.port, clk.pin);
// GPIOPinTypeGPIOOutput(ncs.port, ncs.pin);
//
GPIOPinWrite(miso.port, miso.pin, 0);
GPIOPinWrite(mosi.port, mosi.pin, 0);
GPIOPinWrite(clk.port, clk.pin, 0);
// GPIOPinWrite(ncs.port, ncs.pin, 0);
}
//*****************************************************************************
//
//! Enable the SSI component of the OLED display driver.
//!
//! \param ulFrequency specifies the SSI Clock Frequency to be used.
//!
//! This function initializes the SSI interface to the OLED display.
//!
//! \return None.
//
//*****************************************************************************
void
RIT128x96x4Enable(unsigned long ulFrequency)
{
unsigned long ulTemp;
//
// Disable the SSI port.
//
SSIDisable(SSI0_BASE);
//
// Configure the SSI0 port for master mode.
//
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_2,
SSI_MODE_MASTER, ulFrequency, 8);
//
// (Re)Enable SSI control of the FSS pin.
//
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
//
// Enable the SSI port.
//
SSIEnable(SSI0_BASE);
//
// Drain the receive fifo.
//
while(SSIDataGetNonBlocking(SSI0_BASE, &ulTemp) != 0)
{
}
//
// Indicate that the RIT driver can use the SSI Port.
//
g_bSSIEnabled = true;
}
void Spi::enable(uint32_t mode, uint32_t protocol, uint32_t datawidth, uint32_t baudrate)
{
// Store SPI mode, protoco, baudrate and datawidth
mode_ = mode;
protocol_ = protocol;
baudrate_ = baudrate;
datawidth_ = datawidth;
// Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3)
SysCtrlPeripheralEnable(peripheral_);
SysCtrlPeripheralSleepEnable(peripheral_);
SysCtrlPeripheralDeepSleepDisable(peripheral_);
// Reset peripheral previous to configuring it
SSIDisable(base_);
// Set IO clock as SPI0 clock source
SSIClockSourceSet(base_, clock_);
// Configure the MISO, MOSI, CLK and nCS pins as peripheral
IOCPinConfigPeriphInput(miso_.getPort(), miso_.getPin(), miso_.getIoc());
IOCPinConfigPeriphOutput(mosi_.getPort(), mosi_.getPin(), mosi_.getIoc());
IOCPinConfigPeriphOutput(clk_.getPort(), clk_.getPin(), clk_.getIoc());
// IOCPinConfigPeriphOutput(ncs_.getPort(), ncs_.getPin(), ncs_.getIoc());
// Configure MISO, MOSI, CLK and nCS GPIOs
GPIOPinTypeSSI(miso_.getPort(), miso_.getPin());
GPIOPinTypeSSI(mosi_.getPort(), mosi_.getPin());
GPIOPinTypeSSI(clk_.getPort(), clk_.getPin());
// GPIOPinTypeSSI(ncs_.getPort(), ncs_.getPin());
// Configure the SPI0 clock
SSIConfigSetExpClk(base_, SysCtrlIOClockGet(), protocol_, \
mode_, baudrate_, datawidth_);
// Enable the SPI0 module
SSIEnable(base_);
}
void vs_ssi_speed(unsigned long speed)
{
unsigned long clk;
clk = SysCtlClockGet();
if((speed == 0) ||
(speed > (clk/2)))
{
speed = clk/2;
}
if(speed > SSI_SPEED)
{
speed = SSI_SPEED;
}
SSIDisable(SSI1_BASE);
SSIConfigSetExpClk(SSI1_BASE, clk, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, speed, 8);
SSIEnable(SSI1_BASE);
return;
}
Fd_t spi_Open(char *ifName, unsigned long flags)
{
//
// Enable required SSI and GPIO peripherals.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_IRQ_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_nHIB_PORT);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI);
SysCtlPeripheralEnable(SYSCTL_PERIPH_SPI_BASE);
//
// Set pin muxing to route the SPI signals to the relevant pins.
//
GPIOPinConfigure(SPI_CLK_MUX_SEL);
GPIOPinConfigure(SPI_RX_MUX_SEL);
GPIOPinConfigure(SPI_TX_MUX_SEL);
//GPIOPinConfigure(GPIO_PB5_SSI2FSS);
//
// Configure the appropriate pins to be SSI instead of GPIO
//
GPIOPinTypeSSI(SPI_PORT,(SPI_TX_PIN | SPI_RX_PIN | SPI_CLK_PIN));
//
// Ensure that the SSI is disabled before making any configuration
// changes.
//
SSIDisable(SPI_BASE);
//
// Configure SSI with 8 bit data, Polarity '0', Phase '1' and clock
// frequency of 4Mhz.
//
SSIConfigSetExpClk(SPI_BASE, g_ui32SysClock, SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 4000000, 8);
// Configure CS and nHIB/Enable lines (CS High, nHIB Low)
GPIOPinTypeGPIOOutput(SPI_CS_PORT, SPI_CS_PIN);
GPIOPinTypeGPIOOutput(SPI_GPIO_nHIB_BASE, SPI_nHIB_PIN);
GPIOPinWrite(SPI_GPIO_nHIB_BASE,SPI_nHIB_PIN, PIN_LOW); // not necesary on cc3100
GPIOPinWrite(SPI_CS_PORT,SPI_CS_PIN, PIN_HIGH);
//
// Enable the SSI now that configuration is complete.
//
SSIEnable(SPI_BASE);
//
// configure host IRQ line
//
GPIOPinTypeGPIOInput(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN);
GPIOPadConfigSet(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPD);
GPIOIntTypeSet(SPI_GPIO_IRQ_BASE, SPI_IRQ_PIN, GPIO_RISING_EDGE);
GPIOIntClear(SPI_GPIO_IRQ_BASE,SPI_IRQ_PIN);
GPIOIntDisable(SPI_GPIO_IRQ_BASE,SPI_IRQ_PIN);
IntEnable(INT_GPIO_SPI);
IntMasterEnable();
/* 1 ms delay */
ROM_SysCtlDelay( (g_ui32SysClock/(3*1000))*1 );
/* Enable WLAN interrupt */
CC3100_InterruptEnable();
return NONOS_RET_OK;
}
/**************************************************************************************************
* @fn npSpiInit
*
* @brief This function is called to set up the SPI interface.
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
void npSpiInit(void)
{
uint32 ulDummy;
if (ZNP_CFG1_UART == znpCfg1)
{
return;
}
/* Configure SRDY and deassert SRDY */
GPIOPinTypeGPIOOutput(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN);
GPIOPinWrite(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN, HAL_SPI_SRDY_PIN);
/* Configure MRDY and deassert MRDY */
GPIOPinTypeGPIOInput(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN);
GPIOPinWrite(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN, HAL_SPI_MRDY_PIN);
/* Enable SSI peripheral module */
SysCtrlPeripheralEnable(BSP_SPI_SSI_ENABLE_BM);
/* Delay is essential for this customer */
SysCtrlDelay(32);
/* Configure pin type */
GPIOPinTypeSSI(BSP_SPI_BUS_BASE, (BSP_SPI_MOSI | BSP_SPI_MISO | BSP_SPI_SCK | HAL_SPI_SS_PIN));
/* Map SSI signals to the correct GPIO pins and configure them as HW ctrl'd */
IOCPinConfigPeriphOutput(BSP_SPI_BUS_BASE, BSP_SPI_MISO, IOC_MUX_OUT_SEL_SSI0_TXD);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, BSP_SPI_SCK, IOC_CLK_SSIIN_SSI0);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, BSP_SPI_MOSI, IOC_SSIRXD_SSI0);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, HAL_SPI_SS_PIN, IOC_SSIFSSIN_SSI0);
/* Disable SSI function */
SSIDisable(BSP_SPI_SSI_BASE);
/* Set system clock as SSI clock source */
SSIClockSourceSet(BSP_SPI_SSI_BASE, SSI_CLOCK_SYSTEM);
/* Configure SSI module to Motorola/Freescale SPI mode 3 Slave:
* Polarity = 1, observed in scope from MSP430 master
* Phase = 1, observed in scope from MSP430 master
* Word size = 8 bits
* Clock = 2MHz, observed MSP430 master clock is 2049180Hz
*/
SSIConfigSetExpClk(BSP_SPI_SSI_BASE, SysCtrlClockGet(), SSI_FRF_MOTO_MODE_3,
SSI_MODE_SLAVE, 2000000UL, 8);
/* Register SPI uDMA complete interrupt */
SSIIntRegister(BSP_SPI_SSI_BASE, &npSpiUdmaCompleteIsr);
/* Enable uDMA complete interrupt for SPI RX and TX */
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_RX | SSI_DMA_TX);
/* Configure SPI priority */
IntPrioritySet(INT_SSI0, HAL_INT_PRIOR_SSI0);
IntPrioritySet(INT_GPIOB, HAL_INT_PRIOR_SSI_MRDY);
/* Enable the SSI function */
SSIEnable(BSP_SPI_SSI_BASE);
GPIOIntTypeSet(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN, GPIO_BOTH_EDGES);
GPIOPortIntRegister(HAL_SPI_MRDY_BASE, *npSpiMrdyIsr);
GPIOPinIntEnable(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN);
/* Initialize uDMA for SPI */
npSpiUdmaInit();
}
/*
* ======== SPICC26XXDMA_hwiFxn ========
* ISR for the SPI when we use the UDMA
*/
static void SPICC26XXDMA_hwiFxn (UArg arg) {
SPI_Transaction *msg;
SPICC26XX_Object *object;
SPICC26XX_HWAttrs const *hwAttrs;
uint32_t intStatus;
/* Get the pointer to the object and hwAttrs */
object = ((SPI_Handle)arg)->object;
hwAttrs = ((SPI_Handle)arg)->hwAttrs;
Log_print1(Diags_USER2, "SPI:(%p) interrupt context start", hwAttrs->baseAddr);
/* Get the interrupt status of the SPI controller */
intStatus = SSIIntStatus(hwAttrs->baseAddr, true);
SSIIntClear(hwAttrs->baseAddr, intStatus);
/* Error handling:
* Overrun in the RX Fifo -> at least one sample in the shift
* register has been discarded */
if (intStatus & SSI_RXOR) {
/* disable the interrupt */
SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR);
/* If the RX overrun occurred during a transfer */
if (object->currentTransaction) {
/* Then cancel the ongoing transfer */
SPICC26XXDMA_transferCancel((SPI_Handle)arg);
}
else {
/* Otherwise disable the SPI and DMA modules and flush FIFOs */
SSIDisable(hwAttrs->baseAddr);
/* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Clear out the FIFO by resetting SPI module and re-initting */
HapiResetPeripheral(hwAttrs->baseAddr == SSI0_BASE ? PRCM_PERIPH_SSI0 : PRCM_PERIPH_SSI1);
SPICC26XXDMA_initHw((SPI_Handle)arg);
}
Log_print1(Diags_USER1, "RX FIFO overrun occurred in SPI: (%p) !\n", hwAttrs->baseAddr);
}
else {
/* Determine if the TX DMA channel has completed... */
if (UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->txChannelBitMask)) {
/* Disable SPI TX DMA and clear DMA done interrupt. */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX);
UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->txChannelBitMask);
/* All transfers will set up both TX and RX DMA channels and both will finish.
* Even if the transaction->rxBuf == NULL, it will setup a dummy RX transfer to
* a scratch memory location which is then discarded.
* Therefore all cleanup is only done when the RX DMA channel has completed,
* since it will always run at some point after the TX DMA channel has completed.
*/
}
/* Determine if the RX DMA channel has completed... */
if(UDMACC26XX_channelDone(object->udmaHandle, hwAttrs->rxChannelBitMask)) {
/* Disable SPI RX DMA and clear DMA done interrupt. */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, hwAttrs->rxChannelBitMask);
/* Transaction is complete */
object->currentTransaction->status = SPI_TRANSFER_COMPLETED;
/* Use a temporary transaction pointer in case the callback function
* attempts to perform another SPI_transfer call
*/
msg = object->currentTransaction;
Log_print2(Diags_USER1,"SPI:(%p) DMA transaction: %p complete",
hwAttrs->baseAddr, (UArg)msg);
/* Release constraint since transaction is done */
threadSafeConstraintRelease((uint32_t)(object->currentTransaction->txBuf));
/* Indicate we are done with this transfer */
object->currentTransaction = NULL;
/* Perform callback */
object->transferCallbackFxn((SPI_Handle)arg, msg);
}
}
Log_print1(Diags_USER2, "SPI:(%p) interrupt context end",
hwAttrs->baseAddr);
}
/*!
* @brief Function that cancels a SPI transfer. Will disable SPI and UDMA modules
* and allow standby.
*
* @pre SPICC26XXDMA_open() has to be called first.
* Calling context: Task
*
* @param handle The SPI_Handle for ongoing transaction.
*/
void SPICC26XXDMA_transferCancel(SPI_Handle handle) {
SPICC26XX_Object *object;
SPI_Transaction *msg;
SPICC26XX_HWAttrs const *hwAttrs;
volatile tDMAControlTable *dmaControlTableEntry;
unsigned int key;
/* Get the pointer to the object and hwAttrs */
object = handle->object;
hwAttrs = handle->hwAttrs;
/* Check if a transfer is in progress */
key = Hwi_disable();
/* Check if there is an active transaction */
if(!(object->currentTransaction)) {
Hwi_restore(key);
return;
}
Hwi_restore(key);
/* Disable the SPI module */
SSIDisable(hwAttrs->baseAddr);
/* Disable SPI TX/RX DMA and clear DMA done interrupt just in case it finished */
SSIDMADisable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX);
UDMACC26XX_clearInterrupt(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Disable and clear any pending interrupts */
SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR);
SSIIntClear(hwAttrs->baseAddr, SSI_RXOR);
/* Clear out the FIFO by resetting SPI module and re-initting */
HapiResetPeripheral(hwAttrs->baseAddr == SSI0_BASE ? PRCM_PERIPH_SSI0 : PRCM_PERIPH_SSI1);
SPICC26XXDMA_initHw(handle);
/* Release constraint since transaction is done */
threadSafeConstraintRelease((uint32_t)(object->currentTransaction->txBuf));
/* Mark the transaction as failed if we didn't end up here due to a CSN deassertion */
if (object->currentTransaction->status != SPI_TRANSFER_CSN_DEASSERT) {
object->currentTransaction->status = SPI_TRANSFER_FAILED;
}
/* Disable the UDMA channels */
UDMACC26XX_channelDisable(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Update the SPI_Transaction.count parameter */
/* rxChannel always finishes after txChannel so remaining bytes of the rxChannel is used to update count */
dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaRxControlTableEntry0 : &dmaRxControlTableEntry1);
object->currentTransaction->count -= UDMACC26XX_GET_TRANSFER_SIZE(dmaControlTableEntry->ui32Control);
/* Use a temporary transaction pointer in case the callback function
* attempts to perform another SPI_transfer call
*/
msg = object->currentTransaction;
/* Indicate we are done with this transfer */
object->currentTransaction = NULL;
Log_print2(Diags_USER1,"SPI:(%p) DMA transaction: %p cancelled",
hwAttrs->baseAddr, (UArg)msg);
/* Perform callback */
object->transferCallbackFxn(handle, msg);
/* Transaction was successfully canceled */
return;
}
void main(void) {
uint32_t color = 0;
uint32_t CORD_INDEX;
uint32_t BRIT = 0xFF000000;
uint32_t BLU = 0x00FF0000;
uint32_t GREE =0x0000FF00;
uint32_t RED = 0x000000FF;
// We set the system clock to 16 mHZ
SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_16MHZ);
// enable the SSIO module with this function
// we must also enable GPIO module A, because the SSIO module uses pins A2-A5
SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
// Sets the GPIO pins up, due to the fact they're mux'd
GPIOPinConfigure(GPIO_PA2_SSI0CLK);
GPIOPinConfigure(GPIO_PA3_SSI0FSS);
GPIOPinConfigure(GPIO_PA4_SSI0RX);
GPIOPinConfigure(GPIO_PA5_SSI0TX);
//Sets up pins 5, 4, 3, 2 in
GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 |
GPIO_PIN_2);
// Sets up the SSIO systemcount
// SSI_FRF_MOTO_MODE_0 is chosen, apposed to any other mode, because in the apa102, data is read
// on the rising edge, and propegated on the falling edge.
// This means that data is "loaded" into the register on a rising edge, and set off through the SSI
// on a falling edge I think.
SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_MASTER, 1000000, 16);
SSIEnable(SSI0_BASE);
SSIDataPut(SSI0_BASE, 0);
while(SSIBusy(SSI0_BASE)) {}
SSIDataPut(SSI0_BASE, 0);
while(SSIBusy(SSI0_BASE)) {}
for(CORD_INDEX = 0; CORD_INDEX < 120; ++CORD_INDEX){
if(CORD_INDEX % 2 == 0)
color |= BRIT;
switch(CORD_INDEX % 6){
case(0):
color |= BLU;
break;
case(3):
color |= GREE;
break;
case(5):
color |= RED;
break;
default:
break;
}
SSIDataPut(SSI0_BASE, color);
//wait for things to finish
while(SSIBusy(SSI0_BASE)) {}
if(CORD_INDEX % 2 == 1)
color = 0;
}
for(CORD_INDEX = 0; CORD_INDEX < 2; CORD_INDEX++){
SSIDataPut(SSI0_BASE, 0);
while(SSIBusy(SSI0_BASE)) {}
}
SSIDisable(SSI0_BASE);
return;
}
