int musb_platform_init(void)
{
/* board specific initialization */
board_musb_init();
bfin_anomaly_init();
/* Configure PLL oscillator register */
bfin_write_USB_PLLOSC_CTRL(0x3080 |
((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
SSYNC();
bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
SSYNC();
bfin_write_USB_EP_NI0_RXMAXP(64);
SSYNC();
bfin_write_USB_EP_NI0_TXMAXP(64);
SSYNC();
/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
bfin_write_USB_GLOBINTR(0x7);
SSYNC();
bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
SSYNC();
return 0;
}
int spi_claim_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
spi_portmux(slave);
write_SPI_CTL(bss, bss->ctl);
write_SPI_BAUD(bss, bss->baud);
SSYNC();
return 0;
}
void board_musb_init(void)
{
/*
* Rev 1.0 BF549 EZ-KITs require PE7 to be high for both device
* and OTG host modes, while rev 1.1 and greater require PE7 to
* be low for device mode and high for host mode. We set it high
* here because we are in host mode.
*/
bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7);
bfin_write_PORTE_DIR_SET(PE7);
bfin_write_PORTE_SET(PE7);
SSYNC();
}
void post_init_uart(int sclk)
{
int divisor;
for (divisor = 0; sclk > 0; divisor++)
sclk -= 57600 * 16;
bfin_write_PORTF_FER(0x000F);
bfin_write_PORTH_FER(0xFFFF);
bfin_write_UART_GCTL(0x00);
bfin_write_UART_LCR(0x83);
SSYNC();
bfin_write_UART_DLL(divisor & 0xFF);
SSYNC();
bfin_write_UART_DLH((divisor >> 8) & 0xFF);
SSYNC();
bfin_write_UART_LCR(0x03);
SSYNC();
bfin_write_UART_GCTL(0x01);
SSYNC();
}
void spi_release_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
peripheral_free_list(pins[slave->bus]);
if (is_gpio_cs(slave->cs))
gpio_free(gpio_cs(slave->cs));
write_SPI_CTL(bss, 0);
SSYNC();
}
/*------------------------------------------------------------------------------
* stop the specific DMA channel.
*-----------------------------------------------------------------------------*/
void disable_dma(unsigned int channel)
{
pr_debug("stop_dma() : BEGIN \n");
BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
&& channel < MAX_BLACKFIN_DMA_CHANNEL));
dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
SSYNC();
dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
/* Needs to be enabled Later */
pr_debug("stop_dma() : END \n");
return;
}
void *gpio_cfi_flash_swizzle(void *vaddr)
{
unsigned long addr = (unsigned long)vaddr;
gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
#ifdef GPIO_MASK_2
gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
#endif
SSYNC();
return (void *)(addr & ~GPIO_MASK);
}
static void ipi_cpu_stop(unsigned int cpu)
{
spin_lock(&stop_lock);
printk(KERN_CRIT "CPU%u: stopping\n", cpu);
dump_stack();
spin_unlock(&stop_lock);
set_cpu_online(cpu, false);
local_irq_disable();
while (1)
SSYNC();
}
static void bfin_write(struct map_info *map, map_word d1, unsigned long ofs)
{
struct async_state *state = (struct async_state *)map->map_priv_1;
uint16_t d;
d = d1.x[0];
switch_to_flash(state);
writew(d, map->virt + ofs);
SSYNC();
switch_back(state);
}
void disable_gptimers(uint16_t mask)
{
int i;
uint16_t m = mask;
tassert((mask & ~BLACKFIN_GPTIMER_IDMASK) == 0);
for (i = 0; i < BFIN_TIMER_NUM_GROUP; ++i) {
group_regs[i]->disable = m & 0xFF;
m >>= 8;
}
for (i = 0; i < MAX_BLACKFIN_GPTIMERS; ++i)
if (mask & (1 << i))
group_regs[BFIN_TIMER_OCTET(i)]->status |= trun_mask[i];
SSYNC();
}
static irqreturn_t sport_rx_irq(int irq, void *dev_id)
{
struct sport_device *sport = dev_id;
unsigned long status;
status = get_dma_curr_irqstat(sport->rx_dma_chan);
if (status & (DMA_DONE|DMA_ERR)) {
clear_dma_irqstat(sport->rx_dma_chan);
SSYNC();
}
if (sport->rx_callback)
sport->rx_callback(sport->rx_data);
return IRQ_HANDLED;
}
static int tx09_fb_open(struct fb_info *info, int user)
{
unsigned long flags;
pr_debug("%s\n", __func__);
spin_lock_irqsave(&tx09_lock, flags);
tx09_open_cnt++; /* increase counter */
spin_unlock_irqrestore(&tx09_lock, flags);
if (tx09_open_cnt <= 1) { /* opened the first time */
/* stop PPI */
WRITE_PPI_CONTROL(0);
SSYNC();
/* configure dma stuff */
config_dma();
config_ppi();
/* start dma */
enable_dma(CH_PPI);
SSYNC();
/* start PPI */
WRITE_PPI_CONTROL(READ_PPI_CONTROL() | PORT_EN);
SSYNC();
if (!t_conf_done)
config_timers();
start_timers();
}
return 0;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
if (is_gpio_cs(slave->cs)) {
unsigned int cs = gpio_cs(slave->cs);
gpio_set_value(cs, !bss->cs_pol);
} else {
u32 ssel;
ssel = bfin_read32(&bss->regs->ssel);
if (bss->cs_pol)
ssel &= ~(BIT(8) << slave->cs);
else
ssel |= BIT(8) << slave->cs;
/* deassert cs */
bfin_write32(&bss->regs->ssel, ssel);
SSYNC();
/* disable cs */
ssel &= ~(1 << slave->cs);
bfin_write32(&bss->regs->ssel, ssel);
}
SSYNC();
}
void spi_release_bus(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
peripheral_free_list(pins[slave->bus]);
if (is_gpio_cs(slave->cs))
gpio_free(gpio_cs(slave->cs));
bfin_write32(&bss->regs->rx_control, 0x0);
bfin_write32(&bss->regs->tx_control, 0x0);
bfin_write32(&bss->regs->control, 0x0);
SSYNC();
}
int video_init(void *dst)
{
Init_Ports();
Init_DMA(dst);
EnableDMA();
InitTIMER0();
InitTIMER1();
Init_PPI();
EnablePPI();
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
EnableTIMER1();
/* Add Some Delay ... */
SSYNC();
SSYNC();
SSYNC();
SSYNC();
/* now start frame sync 1 */
EnableTIMER0();
return 0;
}
void enable_dma(unsigned int channel)
{
pr_debug("enable_dma() : BEGIN \n");
BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
&& channel < MAX_BLACKFIN_DMA_CHANNEL));
dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
dma_ch[channel].regs->curr_x_count = 0;
dma_ch[channel].regs->curr_y_count = 0;
dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
SSYNC();
pr_debug("enable_dma() : END \n");
return;
}
void __init setup_system_timer0(void)
{
/* Power down the core timer, just to play safe. */
bfin_write_TCNTL(0);
disable_gptimers(TIMER0bit);
set_gptimer_status(0, TIMER_STATUS_TRUN0);
while (get_gptimer_status(0) & TIMER_STATUS_TRUN0)
udelay(10);
set_gptimer_config(0, 0x59); /* IRQ enable, periodic, PWM_OUT, SCLKed, OUT PAD disabled */
set_gptimer_period(TIMER0_id, get_sclk() / HZ);
set_gptimer_pwidth(TIMER0_id, 1);
SSYNC();
enable_gptimers(TIMER0bit);
}
void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
{
unsigned long ctrl;
int i;
for (i = 0; i < MAX_CPLBS; i++) {
bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
}
ctrl = bfin_read_IMEM_CONTROL();
ctrl |= IMC | ENICPLB;
/* CSYNC to ensure load store ordering */
CSYNC();
bfin_write_IMEM_CONTROL(ctrl);
SSYNC();
}
void post_out_buff(char *buff)
{
int i = 0;
for (i = 0; i < 0x80000; i++)
;
i = 0;
while ((buff[i] != '\0') && (i != 100)) {
while (!(bfin_read_pUART_LSR() & 0x20)) ;
bfin_write_UART_THR(buff[i]);
SSYNC();
i++;
}
for (i = 0; i < 0x80000; i++)
;
}
static int request_ports(void)
{
u16 tmr_req[] = TIMERS;
/*
UD: PF13
MOD: PF10
LBR: PF14
PPI_CLK: PF15
*/
if (peripheral_request_list(ppi_pins, KBUILD_MODNAME)) {
pr_err("requesting PPI peripheral failed\n");
return -EBUSY;
}
if (peripheral_request_list(tmr_req, KBUILD_MODNAME)) {
peripheral_free_list(ppi_pins);
pr_err("requesting timer peripheral failed\n");
return -EBUSY;
}
#if (defined(UD) && defined(LBR))
if (gpio_request_one(UD, GPIOF_OUT_INIT_LOW, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", UD);
return -EBUSY;
}
if (gpio_request_one(LBR, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", LBR);
gpio_free(UD);
return -EBUSY;
}
#endif
if (gpio_request_one(MOD, GPIOF_OUT_INIT_HIGH, KBUILD_MODNAME)) {
pr_err("requesting GPIO %d failed\n", MOD);
#if (defined(UD) && defined(LBR))
gpio_free(LBR);
gpio_free(UD);
#endif
return -EBUSY;
}
SSYNC();
return 0;
}
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
{
if (dcache_status())
blackfin_dcache_flush_range(logo->data,
logo->data + logo->size);
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
/* Setup destination start address */
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
+ (y * LCD_X_RES * LCD_PIXEL_SIZE));
/* Setup destination xcount */
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
/* Setup destination xmodify */
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
/* Setup destination ycount */
bfin_write_MDMA_D0_Y_COUNT(logo->height);
/* Setup destination ymodify */
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
DMA_SIZE16);
/* Setup Source start address */
bfin_write_MDMA_S0_START_ADDR(logo->data);
/* Setup Source xcount */
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
/* Setup Source xmodify */
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
/* Setup Source ycount */
bfin_write_MDMA_S0_Y_COUNT(logo->height);
/* Setup Source ymodify */
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
/* Enable source DMA */
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
SSYNC();
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
| DMA_ERR);
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
| DMA_ERR);
}
static void config_timers(void)
{
unsigned long timer_period = 0;
pr_debug("%s\n", __func__);
/* stop timers */
#ifdef CONFIG_BFIN561_BLUETECHNIX_CM
bfin_write_TMRS8_DISABLE((1 << TIMER_DCLK) | (1 << TIMER_VSYNC) |
(1 << TIMER_BACKLIGHT));
bfin_write_TMRS4_DISABLE((1 << (TIMER_HSYNC - 8)) |
(1 << (TIMER_DTMG - 8)));
#else
bfin_write_TIMER_DISABLE((1 << TIMER_VSYNC) | (1 << TIMER_HSYNC) |
(1 << TIMER_DTMG) | (1 << TIMER_DCLK) |
(1 << TIMER_BACKLIGHT));
#endif
SSYNC();
/* dclk clock output */
BFIN_WRITE(TIMER_DCLK, CONFIG) (PERIOD_CNT | PULSE_HI | PWM_OUT);
timer_period =
get_sclk() / (CONFIG_FB_HITACHI_TX09_REFRESHRATE * 89271);
BFIN_WRITE(TIMER_DCLK, PERIOD) (timer_period);
BFIN_WRITE(TIMER_DCLK, WIDTH) (timer_period / 2);
SSYNC();
/* brightness timer */
BFIN_WRITE(TIMER_BACKLIGHT, CONFIG) (PERIOD_CNT | PULSE_HI | PWM_OUT);
timer_period = get_sclk() / 100000;
BFIN_WRITE(TIMER_BACKLIGHT, PERIOD) (timer_period);
BFIN_WRITE(TIMER_BACKLIGHT, WIDTH) (timer_period - 1); /* 100% duty cycle */
SSYNC();
/* hsync timer */
BFIN_WRITE(TIMER_HSYNC, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT); /* clocked by PPI_clk */
BFIN_WRITE(TIMER_HSYNC, PERIOD) (273); /* 240 + 33 blanking */
BFIN_WRITE(TIMER_HSYNC, WIDTH) (5);
SSYNC();
/* dtmg timer */
BFIN_WRITE(TIMER_DTMG, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT); /* clocked by PPI_clk */
BFIN_WRITE(TIMER_DTMG, PERIOD) (273);
BFIN_WRITE(TIMER_DTMG, WIDTH) (33);
SSYNC();
/* vsync timer */
BFIN_WRITE(TIMER_VSYNC, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT); /* clocked by PPI_clk */
BFIN_WRITE(TIMER_VSYNC, PERIOD) (89271);
BFIN_WRITE(TIMER_VSYNC, WIDTH) (1911);
SSYNC();
t_conf_done = 1;
}
static int __init ezkit_init(void)
{
int ret;
printk(KERN_INFO "%s(): registering device resources\n", __func__);
ret = platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
if (ret < 0)
return ret;
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() | (1 << 12));
SSYNC();
#endif
return spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
}
static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
u32 status;
int ret = 0;
if (data) {
ret = sdh_setup_data(mmc, data);
if (ret)
return ret;
}
ret = sdh_send_cmd(mmc, cmd);
if (ret) {
bfin_write_SDH_COMMAND(0);
bfin_write_DMA_CONFIG(0);
bfin_write_SDH_DATA_CTL(0);
SSYNC();
printf("sending CMD%d failed\n", cmd->cmdidx);
return ret;
}
if (data) {
do {
udelay(1);
status = bfin_read_SDH_STATUS();
} while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
RX_OVERRUN)));
if (status & DAT_TIME_OUT) {
bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
ret = -ETIMEDOUT;
} else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
ret = -ECOMM;
} else
bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
if (ret) {
printf("tranfering data failed\n");
return ret;
}
}
return 0;
}
/**
*
* Function: bfin_config_atapi_gpio
*
* Description: Configures the ATAPI pins for use
*
*/
static int bfin_config_atapi_gpio(struct ata_port *ap)
{
bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4);
bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30);
bfin_write_PORTH_DIR_SET(0x4);
bfin_write_PORTJ_FER(0x7f8);
bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0);
bfin_write_PORTJ_DIR_SET(0x5f8);
bfin_write_PORTJ_DIR_CLEAR(0x200);
bfin_write_PORTJ_INEN(0x200);
bfin_write_PINT2_ASSIGN(0x0707);
bfin_write_PINT2_MASK_SET(0x200);
SSYNC();
return 0;
}
static void bfin_sdh_set_ios(struct mmc *mmc)
{
u16 cfg = 0;
u16 clk_ctl = 0;
if (mmc->bus_width == 4) {
cfg = bfin_read_SDH_CFG();
#ifndef RSI_BLKSZ
cfg &= ~PD_SDDAT3;
#endif
cfg |= PUP_SDDAT3;
bfin_write_SDH_CFG(cfg);
clk_ctl |= WIDE_BUS_4;
}
bfin_write_SDH_CLK_CTL(clk_ctl);
SSYNC();
sdh_set_clk(mmc->clock);
}
static void uart_putc(uint32_t uart_base, const char c)
{
/* send a \r for compatibility */
if (c == '\n')
serial_putc('\r');
WATCHDOG_RESET();
/* wait for the hardware fifo to clear up */
while (!(uart_lsr_read(uart_base) & THRE))
continue;
/* queue the character for transmission */
bfin_write(&pUART->thr, c);
SSYNC();
WATCHDOG_RESET();
}
void spi_cs_activate(struct spi_slave *slave)
{
struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
if (is_gpio_cs(slave->cs)) {
unsigned int cs = gpio_cs(slave->cs);
gpio_set_value(cs, bss->flg);
debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
} else {
write_SPI_FLG(bss,
(read_SPI_FLG(bss) &
~((!bss->flg << 8) << slave->cs)) |
(1 << slave->cs));
debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
}
SSYNC();
}
int musb_platform_init(void)
{
/* board specific initialization */
board_musb_init();
if (ANOMALY_05000346) {
bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
SSYNC();
}
if (ANOMALY_05000347) {
bfin_write_USB_APHY_CNTRL(0x0);
SSYNC();
}
/* Configure PLL oscillator register */
bfin_write_USB_PLLOSC_CTRL(0x30a8);
SSYNC();
bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
SSYNC();
bfin_write_USB_EP_NI0_RXMAXP(64);
SSYNC();
bfin_write_USB_EP_NI0_TXMAXP(64);
SSYNC();
/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
bfin_write_USB_GLOBINTR(0x7);
SSYNC();
bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
SSYNC();
return 0;
}
static int bfin_lq035_fb_release(struct fb_info *info, int user)
{
unsigned long flags;
spin_lock_irqsave(&bfin_lq035_lock, flags);
lq035_open_cnt--;
spin_unlock_irqrestore(&bfin_lq035_lock, flags);
if (lq035_open_cnt <= 0) {
bfin_write_PPI_CONTROL(0);
SSYNC();
disable_dma(CH_PPI);
}
return 0;
}
