/**
* Initializes the system.
* System control registers must be unlocked.
*/
void SYS_Init() {
// TODO: why is SYS_UnlockReg() needed? Should be already unlocked.
SYS_UnlockReg();
// HIRC clock (internal RC 22.1184MHz)
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
// HCLK clock source: HIRC, HCLK source divider: 1
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
// HXT clock (external XTAL 12MHz)
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
// Enable 72MHz optimization
FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ);
// Core clock: PLL
CLK_SetCoreClock(PLL_CLOCK);
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
// SPI0 clock: PCLK0
CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0);
CLK_EnableModuleClock(SPI0_MODULE);
// TMR0 clock: HXT
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0);
CLK_EnableModuleClock(TMR0_MODULE);
// USBD clock
CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3));
CLK_EnableModuleClock(USBD_MODULE);
// Enable USB 3.3V LDO
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
// EADC clock: 72Mhz / 8
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
CLK_EnableModuleClock(EADC_MODULE);
// Enable BOD (reset, 2.2V)
SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V);
// Update system core clock
SystemCoreClockUpdate();
// Initialize dataflash
Dataflash_Init();
// Initialize I/O
Display_SetupSPI();
Button_Init();
ADC_Init();
// Initialize display
Display_Init();
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data;
/* In end of main function, program issued CPU reset and write-protection will be disabled. */
if(SYS_IsRegLocked() == 0)
SYS_LockReg();
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+--------------------------------------------+\n");
printf("| NUC029xEE System Driver Sample Code |\n");
printf("+--------------------------------------------+\n");
if(M32(FLAG_ADDR) == SIGNATURE) {
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS_ReadPDID());
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS_IsRegLocked() == 0) {
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector, and set Brown-Out Detector voltage 2.7V */
SYS_EnableBOD(SYS_BODCR_BOD_INTERRUPT_EN, SYS_BODCR_BOD_VL_2_7V);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Enable Low Voltage Reset function */
SYS_ENABLE_LVR();
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Waiting for message send out */
UART_WAIT_TX_EMPTY(UART0);
/* Switch HCLK clock source to Internal RC 22.1184MHz clock and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
CLK_DisablePLL();
/* Reset CPU */
SYS_ResetCPU();
}
//=========================================================================
//----- (00005D24) --------------------------------------------------------
__myevic__ void DevicesOnOff( int off )
{
if ( off )
{
TIMER_DisableInt( TIMER0 );
TIMER_DisableInt( TIMER1 );
TIMER_DisableInt( TIMER2 );
if ( !gFlags.light_sleep )
{
TIMER_DisableInt( TIMER3 );
}
EADC_Close( EADC );
SetADCState( 1, 0 );
SetADCState( 2, 0 );
SetADCState( 14, 0 );
if ( ISVTCDUAL || ISCUBOID || ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
SetADCState( 3, 0 );
SetADCState( 13, 0 );
if ( ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
SetADCState( 15, 0 );
}
PD7 = 0;
BBC_Configure( BBC_PWMCH_CHARGER, 0 );
PD7 = 0;
if ( ISCUBOID || ISCUBO200 || ISRX200S || ISRX23 )
{
PF2 = 0;
}
}
PC1 = 0;
PC0 = 0;
BBC_Configure( BBC_PWMCH_BUCK, 0 );
if ( !ISVTCDUAL ) PC3 = 0;
PC2 = 0;
BBC_Configure( BBC_PWMCH_BOOST, 0 );
if ( ISCUBO200 || ISRX200S || ISRX23 )
{
PF1 = 0;
}
else if ( ISRX300 )
{
PD1 = 0;
}
else
{
PB7 = 0;
}
GPIO_DisableInt( PD, 0 );
PD0 = 0;
GPIO_SetMode( PD, GPIO_PIN_PIN0_Msk, GPIO_MODE_OUTPUT );
if ( ISRX300 )
{
PF5 = 0;
PF6 = 0;
PA3 = 0;
PA2 = 0;
}
if ( ISVTCDUAL )
{
GPIO_DisableInt( PD, 1 );
PD1 = 0;
GPIO_SetMode( PD, GPIO_PIN_PIN1_Msk, GPIO_MODE_OUTPUT );
}
else if ( !ISCUBOID && !ISCUBO200 && !ISRX200S && !ISRX23 && !ISRX300 )
{
GPIO_DisableInt( PD, 7 );
PD7 = 0;
GPIO_SetMode( PD, GPIO_PIN_PIN7_Msk, GPIO_MODE_OUTPUT );
}
SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE11MFP_Msk|SYS_GPE_MFPH_PE12MFP_Msk|SYS_GPE_MFPH_PE13MFP_Msk);
SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE11MFP_GPIO|SYS_GPE_MFPH_PE12MFP_GPIO|SYS_GPE_MFPH_PE13MFP_GPIO);
PE11 = 0;
GPIO_SetMode( PE, GPIO_PIN_PIN11_Msk, GPIO_MODE_OUTPUT );
PE12 = 0;
GPIO_SetMode( PE, GPIO_PIN_PIN12_Msk, GPIO_MODE_OUTPUT );
PE13 = 0;
GPIO_SetMode( PE, GPIO_PIN_PIN13_Msk, GPIO_MODE_OUTPUT );
PE10 = 0;
GPIO_EnableInt( PE, 0, GPIO_INT_BOTH_EDGE );
GPIO_EnableInt( PD, 2, GPIO_INT_BOTH_EDGE );
GPIO_EnableInt( PD, 3, GPIO_INT_BOTH_EDGE );
if ( ISVTCDUAL )
{
PA3 = 0;
PC3 = 0;
PF2 = 0;
PA2 = 0;
}
else if ( ISCUBOID || ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
PF0 = 0;
}
SYS_UnlockReg();
SYS->USBPHY &= ~SYS_USBPHY_LDO33EN_Msk;
SYS->IVSCTL &= ~(SYS_IVSCTL_VBATUGEN_Msk|SYS_IVSCTL_VTEMPEN_Msk);
SYS_DisableBOD();
SYS->VREFCTL = 0;
SYS_LockReg();
USBD_CLR_INT_FLAG( USBD_INTSTS_WAKEUP|USBD_INTSTS_FLDET|USBD_INTSTS_BUS|USBD_INTSTS_USB );
USBD_ENABLE_INT( USBD_INT_WAKEUP );
}
else
{
USBD_CLR_INT_FLAG( USBD_INTSTS_WAKEUP );
SYS_UnlockReg();
SYS->USBPHY |= SYS_USBPHY_LDO33EN_Msk;
SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk;
if ( ISRX300 )
{
SYS->IVSCTL |= SYS_IVSCTL_VTEMPEN_Msk;
}
SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V;
SYS_EnableBOD( SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V );
SYS_LockReg();
GPIO_DisableInt( PE, 0 );
GPIO_DisableInt( PD, 2 );
GPIO_DisableInt( PD, 3 );
if ( ISCUBOID || ISCUBO200 || ISRX200S || ISRX23 )
{
PF2 = 1;
}
SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE11MFP_Msk|SYS_GPE_MFPH_PE12MFP_Msk|SYS_GPE_MFPH_PE13MFP_Msk);
SYS->GPE_MFPH |= (SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0|SYS_GPE_MFPH_PE12MFP_SPI0_SS|SYS_GPE_MFPH_PE13MFP_SPI0_CLK);
GPIO_SetMode( PD, GPIO_PIN_PIN0_Msk, GPIO_MODE_INPUT );
GPIO_EnableInt( PD, 0, GPIO_INT_FALLING );
if ( ISVTCDUAL )
{
GPIO_SetMode( PD, GPIO_PIN_PIN1_Msk, GPIO_MODE_INPUT );
GPIO_EnableInt( PD, 1, GPIO_INT_RISING );
GPIO_ENABLE_DEBOUNCE( PD, GPIO_PIN_PIN1_Msk );
}
else if ( !ISCUBOID && !ISCUBO200 && !ISRX200S && !ISRX23 && !ISRX300 )
{
GPIO_SetMode( PD, GPIO_PIN_PIN7_Msk, GPIO_MODE_INPUT );
GPIO_EnableInt( PD, 7, GPIO_INT_RISING );
GPIO_ENABLE_DEBOUNCE( PD, GPIO_PIN_PIN7_Msk );
}
if ( ISCUBO200 || ISRX200S || ISRX23 )
{
PF1 = 1;
}
else if ( ISRX300 )
{
PD1 = 1;
}
else
{
PB7 = 1;
}
SetADCState( 1, 1 );
SetADCState( 2, 1 );
SetADCState( 14, 1 );
if ( ISVTCDUAL || ISCUBOID || ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
SetADCState( 3, 1 );
SetADCState( 13, 1 );
if ( ISCUBO200 || ISRX200S || ISRX23 || ISRX300 )
{
SetADCState( 15, 1 );
}
}
TIMER_EnableInt( TIMER0 );
TIMER_EnableInt( TIMER1 );
TIMER_EnableInt( TIMER2 );
TIMER_EnableInt( TIMER3 );
}
}
int32_t main (void)
{
uint32_t u32data;
/* HCLK will be set to 42MHz in SYS_Init(void)*/
if(SYS->RegLockAddr == 1) // In end of main function, program issued CPU reset and write-protection will be disabled.
SYS_LockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+----------------------------------------+\n");
printf("| Nano100 System Driver Sample Code |\n");
printf("+----------------------------------------+\n");
if (M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
GetChar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector and power down settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if (SYS->RegLockAddr != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.5V ,
Enable Brown-Out Interrupt function */
SYS_EnableBOD(SYS_BODCTL_BOD25_INT_EN_Msk,SYS_BODCTL_BOD25_EN_Msk);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Waiting for message send out */
// _UART_WAIT_TX_EMPTY(UART0);
/* Enable CKO and output frequency = system clock / 4 */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK,1);
/* Switch HCLK clock source to Internal 11.0592MHz */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1));
/* Enable WDT clock */
CLK_EnableModuleClock(WDT_MODULE);
/* Enable WDT and interrupt */
WDT->CTL = 0x00000050 | 0x00000004 | 0x00000008;
WDT->IER |= 0x00000001;
NVIC_EnableIRQ(WDT_IRQn);
CLK->PWRCTL |= CLK_PWRCTL_WAKEINT_EN; /* Enable wake up interrupt source */
NVIC_EnableIRQ(PDWU_IRQn); /* Enable IRQ request for PDWU interrupt */
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
printf("Enter Power Down Mode >>>>>>>>>>>\n");
u32PWDU_WakeFlag = 0; /* clear software semaphore */
while(!(UART0->FSR & UART_FSR_TX_EMPTY_F_Msk)) ; /* waits for message send out */
CLK_PowerDown();
/* CPU Reset test */
printf("Waits for 5 times WDT interrupts.....\n");
while (u32WDT_Ticks <= 5);
printf("<<<<<<<<<< Program resumes execution.\n");
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Reset CPU */
SYS_ResetCPU();
}
//=========================================================================
//----- (0000652C) --------------------------------------------------------
void InitDevices()
{
SYS_UnlockReg();
// Internal 22.1184MHz oscillator
CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk );
CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk );
CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK( 1 ) );
// 12.000MHz external crystal
CLK_EnableXtalRC( CLK_PWRCTL_HXTEN_Msk );
CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk );
// FMC Frequency Optimisation mode <= 72MHz
FMC_EnableFreqOptimizeMode( FMC_FTCTL_OPTIMIZE_72MHZ );
// Setup PLL to 144MHz and HCLK source to PLL/2
CLK_SetCoreClock( CPU_FREQ );
// UART0 CLK = HXT/1
#if (ENABLE_UART)
CLK_EnableModuleClock( UART0_MODULE );
CLK_SetModuleClock( UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART( 1 ) );
#endif
// USB CLK = PLL/3 (48MHz)
CLK_EnableModuleClock( USBD_MODULE );
CLK_SetModuleClock( USBD_MODULE, 0, CLK_CLKDIV0_USB( 3 ) );
SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk;
// WDT CLK = LIRC/1
CLK_EnableModuleClock( WDT_MODULE );
CLK_SetModuleClock( WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0 );
// SPI0 CLK = PCLK0/1
CLK_EnableModuleClock( SPI0_MODULE );
// EADC CLK = PCLK1/8 (9MHz)
CLK_EnableModuleClock( EADC_MODULE );
CLK_SetModuleClock( EADC_MODULE, 0, CLK_CLKDIV0_EADC( 8 ) );
// CRC CLK = HCLK/1
CLK_EnableModuleClock( CRC_MODULE );
// TIMERS CLOCKS
CLK_EnableModuleClock( TMR0_MODULE );
CLK_EnableModuleClock( TMR1_MODULE );
CLK_EnableModuleClock( TMR2_MODULE );
CLK_EnableModuleClock( TMR3_MODULE );
CLK_SetModuleClock( TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0 );
CLK_SetModuleClock( TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0 );
CLK_SetModuleClock( TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HIRC, 0 );
CLK_SetModuleClock( TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, 0 );
// Enable battery voltage sampling by ADC
SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk;
// ADC reference voltage
SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V;
// Brown-out detector; interrupts under 2.2V
SYS_EnableBOD( SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V );
// Update clock data
SystemCoreClockUpdate();
WDT_Open( WDT_TIMEOUT_2POW18, WDT_RESET_DELAY_18CLK, TRUE, FALSE );
SYS_LockReg();
}
