/**
* Emit function for r600_cs_shader_state atom
*/
void evergreen_emit_cs_shader(
struct r600_context *rctx,
struct r600_atom *atom)
{
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
struct radeon_winsys_cs *cs = rctx->cs;
uint64_t va;
va = r600_resource_va(&rctx->screen->screen, &shader->shader_code_bo->b.b);
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
r600_write_value(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
r600_write_value(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
S_0288D4_NUM_GPRS(shader->bc.ngpr)
| S_0288D4_STACK_SIZE(shader->bc.nstack));
r600_write_value(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
r600_write_value(cs, PKT3C(PKT3_NOP, 0, 0));
r600_write_value(cs, r600_context_bo_reloc(rctx, shader->shader_code_bo,
RADEON_USAGE_READ));
rctx->flags |= R600_CONTEXT_SHADERCONST_FLUSH;
}
/**
* Emit function for r600_cs_shader_state atom
*/
void evergreen_emit_cs_shader(struct r600_context *rctx,
struct r600_atom *atom)
{
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
uint64_t va;
struct r600_resource *code_bo;
unsigned ngpr, nstack;
code_bo = shader->code_bo;
va = shader->code_bo->gpu_address + state->pc;
ngpr = shader->bc.ngpr;
nstack = shader->bc.nstack;
radeon_compute_set_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
S_0288D4_NUM_GPRS(ngpr)
| S_0288D4_STACK_SIZE(nstack));
radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
code_bo, RADEON_USAGE_READ,
RADEON_PRIO_USER_SHADER));
}
static void evergreen_bind_compute_state(struct pipe_context *ctx_, void *state)
{
struct r600_context *ctx = (struct r600_context *)ctx_;
ctx->cs_shader = (struct r600_pipe_compute *)state;
assert(!ctx->cs_shader->shader_code_bo);
ctx->cs_shader->shader_code_bo =
r600_compute_buffer_alloc_vram(ctx->screen,
ctx->cs_shader->bc.ndw * 4);
void *p = ctx->ws->buffer_map(ctx->cs_shader->shader_code_bo->cs_buf,
ctx->cs, PIPE_TRANSFER_WRITE);
memcpy(p, ctx->cs_shader->bc.bytecode, ctx->cs_shader->bc.ndw * 4);
ctx->ws->buffer_unmap(ctx->cs_shader->shader_code_bo->cs_buf);
evergreen_compute_init_config(ctx);
struct evergreen_compute_resource* res = get_empty_res(ctx->cs_shader,
COMPUTE_RESOURCE_SHADER, 0);
if (ctx->chip_class < CAYMAN) {
evergreen_reg_set(res, R_008C0C_SQ_GPR_RESOURCE_MGMT_3,
S_008C0C_NUM_LS_GPRS(ctx->cs_shader->bc.ngpr));
}
///maybe we can use it later
evergreen_reg_set(res, R_0286C8_SPI_THREAD_GROUPING, 0);
///maybe we can use it later
evergreen_reg_set(res, R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2, 0);
evergreen_reg_set(res, R_0288D4_SQ_PGM_RESOURCES_LS,
S_0288D4_NUM_GPRS(ctx->cs_shader->bc.ngpr)
| S_0288D4_STACK_SIZE(ctx->cs_shader->bc.nstack));
evergreen_reg_set(res, R_0288D8_SQ_PGM_RESOURCES_LS_2, 0);
evergreen_reg_set(res, R_0288D0_SQ_PGM_START_LS, 0);
res->bo = ctx->cs_shader->shader_code_bo;
res->usage = RADEON_USAGE_READ;
res->coher_bo_size = ctx->cs_shader->bc.ndw*4;
res->flags = COMPUTE_RES_SH_FLUSH;
/* We can't always determine the
* number of iterations in a loop before it's executed,
* so we just need to set up the loop counter to give us the maximum
* number of iterations possible. Currently, loops in shader code
* ignore the loop counter and use a break instruction to exit the
* loop at the correct time.
*/
evergreen_set_loop_const(ctx->cs_shader,
0, /* index */
0xFFF, /* Maximum value of the loop counter (i.e. when the loop
* counter reaches this value, the program will break
* out of the loop. */
0x0, /* Starting value of the loop counter. */
0x1); /* Amount to increment the loop counter each iteration. */
}
/**
* Emit function for r600_cs_shader_state atom
*/
void evergreen_emit_cs_shader(
struct r600_context *rctx,
struct r600_atom *atom)
{
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint64_t va;
struct r600_resource *code_bo;
unsigned ngpr, nstack;
#if HAVE_LLVM < 0x0306
struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
code_bo = kernel->code_bo;
va = kernel->code_bo->gpu_address;
ngpr = kernel->bc.ngpr;
nstack = kernel->bc.nstack;
#else
code_bo = shader->code_bo;
va = shader->code_bo->gpu_address + state->pc;
ngpr = shader->bc.ngpr;
nstack = shader->bc.nstack;
#endif
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
S_0288D4_NUM_GPRS(ngpr)
| S_0288D4_STACK_SIZE(nstack));
radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
code_bo, RADEON_USAGE_READ,
RADEON_PRIO_SHADER_DATA));
}
/**
* Emit function for r600_cs_shader_state atom
*/
void evergreen_emit_cs_shader(
struct r600_context *rctx,
struct r600_atom *atom)
{
struct r600_cs_shader_state *state =
(struct r600_cs_shader_state*)atom;
struct r600_pipe_compute *shader = state->shader;
struct r600_kernel *kernel = &shader->kernels[state->kernel_index];
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
uint64_t va;
va = r600_resource_va(&rctx->screen->b.b, &kernel->code_bo->b.b);
r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3);
radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */
radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */
S_0288D4_NUM_GPRS(kernel->bc.ngpr)
| S_0288D4_STACK_SIZE(kernel->bc.nstack));
radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */
radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0));
radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx,
kernel->code_bo, RADEON_USAGE_READ));
}
