static void SetSpecialRegValue(int reg, u32 value) { switch (reg) { case 0: PowerPC::ppcState.pc = value; break; case 1: PowerPC::ppcState.spr[SPR_LR] = value; break; case 2: PowerPC::ppcState.spr[SPR_CTR] = value; break; case 3: SetCR(value); break; case 4: PowerPC::ppcState.fpscr = value; break; case 5: PowerPC::ppcState.msr = value; break; case 6: PowerPC::ppcState.spr[SPR_SRR0] = value; break; case 7: PowerPC::ppcState.spr[SPR_SRR1] = value; break; case 8: PowerPC::ppcState.Exceptions = value; break; // Should we just change the value, or use ProcessorInterface::SetInterrupt() to make the system aware? // case 9: return ProcessorInterface::GetMask(); // case 10: return ProcessorInterface::GetCause(); default: return; } }
void RegisterWidget::PopulateTable() { for (int i = 0; i < 32; i++) { // General purpose registers (int) AddRegister(i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return GPR(i); }, [i](u64 value) { GPR(i) = value; }); // Floating point registers (double) AddRegister(i, 2, RegisterType::fpr, "f" + std::to_string(i), [i] { return riPS0(i); }, [i](u64 value) { riPS0(i) = value; }); AddRegister(i, 4, RegisterType::fpr, "", [i] { return riPS1(i); }, [i](u64 value) { riPS1(i) = value; }); } for (int i = 0; i < 8; i++) { // IBAT registers AddRegister(i, 5, RegisterType::ibat, "IBAT" + std::to_string(i), [i] { return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) + PowerPC::ppcState.spr[SPR_IBAT0L + i * 2]; }, nullptr); // DBAT registers AddRegister(i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i), [i] { return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) + PowerPC::ppcState.spr[SPR_DBAT0L + i * 2]; }, nullptr); // Graphics quantization registers AddRegister(i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i), [i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr); } for (int i = 0; i < 16; i++) { // SR registers AddRegister(i, 7, RegisterType::sr, "SR" + std::to_string(i), [i] { return PowerPC::ppcState.sr[i]; }, [i](u64 value) { PowerPC::ppcState.sr[i] = value; }); } // Special registers // TB AddRegister(16, 5, RegisterType::tb, "TB", [] { return static_cast<u64>(PowerPC::ppcState.spr[SPR_TU]) << 32 | PowerPC::ppcState.spr[SPR_TL]; }, nullptr); // PC AddRegister(17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; }, [](u64 value) { PowerPC::ppcState.pc = value; }); // LR AddRegister(18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; }); // CTR AddRegister(19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; }); // CR AddRegister(20, 5, RegisterType::cr, "CR", [] { return GetCR(); }, [](u64 value) { SetCR(value); }); // XER AddRegister(21, 5, RegisterType::xer, "XER", [] { return GetXER().Hex; }, [](u64 value) { SetXER(UReg_XER(value)); }); // FPSCR AddRegister(22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr; }, [](u64 value) { PowerPC::ppcState.fpscr = value; }); // MSR AddRegister(23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr; }, [](u64 value) { PowerPC::ppcState.msr = value; }); // SRR 0-1 AddRegister(24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; }); AddRegister(25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; }); // Exceptions AddRegister(26, 5, RegisterType::exceptions, "Exceptions", [] { return PowerPC::ppcState.Exceptions; }, [](u64 value) { PowerPC::ppcState.Exceptions = value; }); // Int Mask AddRegister(27, 5, RegisterType::int_mask, "Int Mask", [] { return ProcessorInterface::GetMask(); }, nullptr); // Int Cause AddRegister(28, 5, RegisterType::int_cause, "Int Cause", [] { return ProcessorInterface::GetCause(); }, nullptr); // DSISR AddRegister(29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; }); // DAR AddRegister(30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; }, [](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; }); // Hash Mask AddRegister( 31, 5, RegisterType::pt_hashmask, "Hash Mask", [] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; }, nullptr); emit RequestTableUpdate(); m_table->resizeColumnsToContents(); }