/**
* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
* @adapter: pointer to our private adapter structure
*
* FIXME: lot of dups with MAC code
*
* Returns 0 on success, errno on failure
*/
int et131x_set_packet_filter(struct et131x_adapter *adapter)
{
int status = 0;
uint32_t filter = adapter->PacketFilter;
u32 ctrl;
u32 pf_ctrl;
ctrl = readl(&adapter->regs->rxmac.ctrl);
pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
/* Default to disabled packet filtering. Enable it in the individual
* case statements that require the device to filter something
*/
ctrl |= 0x04;
/* Set us to be in promiscuous mode so we receive everything, this
* is also true when we get a packet filter of 0
*/
if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
pf_ctrl &= ~7; /* Clear filter bits */
else {
/*
* Set us up with Multicast packet filtering. Three cases are
* possible - (1) we have a multi-cast list, (2) we receive ALL
* multicast entries or (3) we receive none.
*/
if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
pf_ctrl &= ~2; /* Multicast filter bit */
else {
SetupDeviceForMulticast(adapter);
pf_ctrl |= 2;
ctrl &= ~0x04;
}
/* Set us up with Unicast packet filtering */
if (filter & ET131X_PACKET_TYPE_DIRECTED) {
SetupDeviceForUnicast(adapter);
pf_ctrl |= 4;
ctrl &= ~0x04;
}
/* Set us up with Broadcast packet filtering */
if (filter & ET131X_PACKET_TYPE_BROADCAST) {
pf_ctrl |= 1; /* Broadcast filter bit */
ctrl &= ~0x04;
} else
pf_ctrl &= ~1;
/* Setup the receive mac configuration registers - Packet
* Filter control + the enable / disable for packet filter
* in the control reg.
*/
writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
writel(ctrl, &adapter->regs->rxmac.ctrl);
}
return status;
}
void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
{
struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;
RXMAC_WOL_SA_LO_t sa_lo;
RXMAC_WOL_SA_HI_t sa_hi;
RXMAC_PF_CTRL_t pf_ctrl = { 0 };
DBG_ENTER(et131x_dbginfo);
/* Disable the MAC while it is being configured (also disable WOL) */
writel(0x8, &pRxMac->ctrl.value);
/* Initialize WOL to disabled. */
writel(0, &pRxMac->crc0.value);
writel(0, &pRxMac->crc12.value);
writel(0, &pRxMac->crc34.value);
/* We need to set the WOL mask0 - mask4 next. We initialize it to
* its default Values of 0x00000000 because there are not WOL masks
* as of this time.
*/
writel(0, &pRxMac->mask0_word0);
writel(0, &pRxMac->mask0_word1);
writel(0, &pRxMac->mask0_word2);
writel(0, &pRxMac->mask0_word3);
writel(0, &pRxMac->mask1_word0);
writel(0, &pRxMac->mask1_word1);
writel(0, &pRxMac->mask1_word2);
writel(0, &pRxMac->mask1_word3);
writel(0, &pRxMac->mask2_word0);
writel(0, &pRxMac->mask2_word1);
writel(0, &pRxMac->mask2_word2);
writel(0, &pRxMac->mask2_word3);
writel(0, &pRxMac->mask3_word0);
writel(0, &pRxMac->mask3_word1);
writel(0, &pRxMac->mask3_word2);
writel(0, &pRxMac->mask3_word3);
writel(0, &pRxMac->mask4_word0);
writel(0, &pRxMac->mask4_word1);
writel(0, &pRxMac->mask4_word2);
writel(0, &pRxMac->mask4_word3);
/* Lets setup the WOL Source Address */
sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];
sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];
sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];
sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];
writel(sa_lo.value, &pRxMac->sa_lo.value);
sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];
sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];
writel(sa_hi.value, &pRxMac->sa_hi.value);
/* Disable all Packet Filtering */
writel(0, &pRxMac->pf_ctrl.value);
/* Let's initialize the Unicast Packet filtering address */
if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
SetupDeviceForUnicast(pAdapter);
pf_ctrl.bits.filter_uni_en = 1;
} else {
writel(0, &pRxMac->uni_pf_addr1.value);
writel(0, &pRxMac->uni_pf_addr2.value);
writel(0, &pRxMac->uni_pf_addr3.value);
}
/* Let's initialize the Multicast hash */
if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
pf_ctrl.bits.filter_multi_en = 0;
} else {
pf_ctrl.bits.filter_multi_en = 1;
SetupDeviceForMulticast(pAdapter);
}
/* Runt packet filtering. Didn't work in version A silicon. */
pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
pf_ctrl.bits.filter_frag_en = 1;
if (pAdapter->RegistryJumboPacket > 8192) {
RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
/* In order to transmit jumbo packets greater than 8k, the
* FIFO between RxMAC and RxDMA needs to be reduced in size
* to (16k - Jumbo packet size). In order to implement this,
* we must use "cut through" mode in the RxMAC, which chops
* packets down into segments which are (max_size * 16). In
* this case we selected 256 bytes, since this is the size of
* the PCI-Express TLP's that the 1310 uses.
*/
mcif_ctrl_max_seg.bits.seg_en = 0x1;
mcif_ctrl_max_seg.bits.fc_en = 0x0;
mcif_ctrl_max_seg.bits.max_size = 0x10;
writel(mcif_ctrl_max_seg.value,
&pRxMac->mcif_ctrl_max_seg.value);
} else {
writel(0, &pRxMac->mcif_ctrl_max_seg.value);
}
/* Initialize the MCIF water marks */
writel(0, &pRxMac->mcif_water_mark.value);
/* Initialize the MIF control */
writel(0, &pRxMac->mif_ctrl.value);
/* Initialize the Space Available Register */
writel(0, &pRxMac->space_avail.value);
/* Initialize the the mif_ctrl register
* bit 3: Receive code error. One or more nibbles were signaled as
* errors during the reception of the packet. Clear this
* bit in Gigabit, set it in 100Mbit. This was derived
* experimentally at UNH.
* bit 4: Receive CRC error. The packet's CRC did not match the
* internally generated CRC.
* bit 5: Receive length check error. Indicates that frame length
* field value in the packet does not match the actual data
* byte length and is not a type field.
* bit 16: Receive frame truncated.
* bit 17: Drop packet enable
*/
if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
writel(0x30038, &pRxMac->mif_ctrl.value);
} else {
writel(0x30030, &pRxMac->mif_ctrl.value);
}
/* Finally we initialize RxMac to be enabled & WOL disabled. Packet
* filter is always enabled since it is where the runt packets are
* supposed to be dropped. For version A silicon, runt packet
* dropping doesn't work, so it is disabled in the pf_ctrl register,
* but we still leave the packet filter on.
*/
writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
writel(0x9, &pRxMac->ctrl.value);
DBG_LEAVE(et131x_dbginfo);
}
void ConfigRxMacRegs(struct et131x_adapter *etdev)
{
struct _RXMAC_t __iomem *pRxMac = &etdev->regs->rxmac;
RXMAC_WOL_SA_LO_t sa_lo;
RXMAC_WOL_SA_HI_t sa_hi;
RXMAC_PF_CTRL_t pf_ctrl = { 0 };
writel(0x8, &pRxMac->ctrl.value);
writel(0, &pRxMac->crc0.value);
writel(0, &pRxMac->crc12.value);
writel(0, &pRxMac->crc34.value);
writel(0, &pRxMac->mask0_word0);
writel(0, &pRxMac->mask0_word1);
writel(0, &pRxMac->mask0_word2);
writel(0, &pRxMac->mask0_word3);
writel(0, &pRxMac->mask1_word0);
writel(0, &pRxMac->mask1_word1);
writel(0, &pRxMac->mask1_word2);
writel(0, &pRxMac->mask1_word3);
writel(0, &pRxMac->mask2_word0);
writel(0, &pRxMac->mask2_word1);
writel(0, &pRxMac->mask2_word2);
writel(0, &pRxMac->mask2_word3);
writel(0, &pRxMac->mask3_word0);
writel(0, &pRxMac->mask3_word1);
writel(0, &pRxMac->mask3_word2);
writel(0, &pRxMac->mask3_word3);
writel(0, &pRxMac->mask4_word0);
writel(0, &pRxMac->mask4_word1);
writel(0, &pRxMac->mask4_word2);
writel(0, &pRxMac->mask4_word3);
sa_lo.bits.sa3 = etdev->CurrentAddress[2];
sa_lo.bits.sa4 = etdev->CurrentAddress[3];
sa_lo.bits.sa5 = etdev->CurrentAddress[4];
sa_lo.bits.sa6 = etdev->CurrentAddress[5];
writel(sa_lo.value, &pRxMac->sa_lo.value);
sa_hi.bits.sa1 = etdev->CurrentAddress[0];
sa_hi.bits.sa2 = etdev->CurrentAddress[1];
writel(sa_hi.value, &pRxMac->sa_hi.value);
writel(0, &pRxMac->pf_ctrl.value);
if (etdev->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
SetupDeviceForUnicast(etdev);
pf_ctrl.bits.filter_uni_en = 1;
} else {
writel(0, &pRxMac->uni_pf_addr1.value);
writel(0, &pRxMac->uni_pf_addr2.value);
writel(0, &pRxMac->uni_pf_addr3.value);
}
if (etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
pf_ctrl.bits.filter_multi_en = 0;
} else {
pf_ctrl.bits.filter_multi_en = 1;
SetupDeviceForMulticast(etdev);
}
pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
pf_ctrl.bits.filter_frag_en = 1;
if (etdev->RegistryJumboPacket > 8192) {
RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
mcif_ctrl_max_seg.bits.seg_en = 0x1;
mcif_ctrl_max_seg.bits.fc_en = 0x0;
mcif_ctrl_max_seg.bits.max_size = 0x10;
writel(mcif_ctrl_max_seg.value,
&pRxMac->mcif_ctrl_max_seg.value);
} else {
writel(0, &pRxMac->mcif_ctrl_max_seg.value);
}
writel(0, &pRxMac->mcif_water_mark.value);
writel(0, &pRxMac->mif_ctrl.value);
writel(0, &pRxMac->space_avail.value);
if (etdev->linkspeed == TRUEPHY_SPEED_100MBPS)
writel(0x30038, &pRxMac->mif_ctrl.value);
else
writel(0x30030, &pRxMac->mif_ctrl.value);
writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
writel(0x9, &pRxMac->ctrl.value);
}
/**
* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
* @adapter: pointer to our private adapter structure
*
* Returns 0 on success, errno on failure
*/
int et131x_set_packet_filter(struct et131x_adapter *adapter)
{
int status = 0;
uint32_t filter = adapter->PacketFilter;
RXMAC_CTRL_t ctrl;
RXMAC_PF_CTRL_t pf_ctrl;
DBG_ENTER(et131x_dbginfo);
ctrl.value = readl(&adapter->CSRAddress->rxmac.ctrl.value);
pf_ctrl.value = readl(&adapter->CSRAddress->rxmac.pf_ctrl.value);
/* Default to disabled packet filtering. Enable it in the individual
* case statements that require the device to filter something
*/
ctrl.bits.pkt_filter_disable = 1;
/* Set us to be in promiscuous mode so we receive everything, this
* is also true when we get a packet filter of 0
*/
if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) {
pf_ctrl.bits.filter_broad_en = 0;
pf_ctrl.bits.filter_multi_en = 0;
pf_ctrl.bits.filter_uni_en = 0;
} else {
/*
* Set us up with Multicast packet filtering. Three cases are
* possible - (1) we have a multi-cast list, (2) we receive ALL
* multicast entries or (3) we receive none.
*/
if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
DBG_VERBOSE(et131x_dbginfo,
"Multicast filtering OFF (Rx ALL MULTICAST)\n");
pf_ctrl.bits.filter_multi_en = 0;
} else {
DBG_VERBOSE(et131x_dbginfo, "Multicast filtering ON\n");
SetupDeviceForMulticast(adapter);
pf_ctrl.bits.filter_multi_en = 1;
ctrl.bits.pkt_filter_disable = 0;
}
/* Set us up with Unicast packet filtering */
if (filter & ET131X_PACKET_TYPE_DIRECTED) {
DBG_VERBOSE(et131x_dbginfo, "Unicast Filtering ON\n");
SetupDeviceForUnicast(adapter);
pf_ctrl.bits.filter_uni_en = 1;
ctrl.bits.pkt_filter_disable = 0;
}
/* Set us up with Broadcast packet filtering */
if (filter & ET131X_PACKET_TYPE_BROADCAST) {
DBG_VERBOSE(et131x_dbginfo, "Broadcast Filtering ON\n");
pf_ctrl.bits.filter_broad_en = 1;
ctrl.bits.pkt_filter_disable = 0;
} else {
DBG_VERBOSE(et131x_dbginfo,
"Broadcast Filtering OFF\n");
pf_ctrl.bits.filter_broad_en = 0;
}
/* Setup the receive mac configuration registers - Packet
* Filter control + the enable / disable for packet filter
* in the control reg.
*/
writel(pf_ctrl.value,
&adapter->CSRAddress->rxmac.pf_ctrl.value);
writel(ctrl.value, &adapter->CSRAddress->rxmac.ctrl.value);
}
DBG_LEAVE(et131x_dbginfo);
return status;
}
