IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
{
return;
}
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
SysDisableSGXInterrupts(psSysData);
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
{
int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
}
}
omap_device_set_rate(&gpsPVRLDMDev->dev,
&gpsPVRLDMDev->dev, 0);
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
}
IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
return;
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
SysDisableSGXInterrupts(psSysData);
#if defined(SYS_XB47_HAS_DVFS_FRAMEWORK)
{
struct gpu_platform_data *pdata;
int res;
pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data;
if (psSysSpecData->ui32SGXFreqListIndex != 0)
{
PVR_ASSERT(pdata->device_scale != IMG_NULL);
res = pdata->device_scale(&gpsPVRLDMDev->dev,
&gpsPVRLDMDev->dev,
psSysSpecData->pui32SGXFreqList[0]);
if (res == 0)
{
psSysSpecData->ui32SGXFreqListIndex = 0;
}
else if (res == -EBUSY)
{
PVR_DPF((PVR_DBG_WARNING, "DisableSGXClocks: Unable to scale SGX frequency (EBUSY)"));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
else if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: Unable to scale SGX frequency (%d)", res));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
}
}
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
}
IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
{
return;
}
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
SysDisableSGXInterrupts(psSysData);
#if defined(MTK_USE_GDC)
SysDeInitGDC();
#endif
DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)&~4);
disable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
disable_clock(MT65XX_PDN_MM_MFG, "MFG");
disable_clock(MT65XX_PDN_MM_G3D, "MFG");
//DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)&~4);
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) && defined(CONFIG_PM_RUNTIME)
{
int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
}
}
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
}
/*!
******************************************************************************
@Function DisableSGXClocks
@Description Disable SGX clocks.
@Return none
******************************************************************************/
IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
int i;
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
/* SGX clocks already disabled? */
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
{
return;
}
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
SysDisableSGXInterrupts(psSysData);
for(i = sizeof(clk_data)/sizeof(clk_data[0]) - 1; i >= 0; i--)
{
clk_disable_unprepare(clk_data[i].clk_handle);
}
#if defined(LDM_PLATFORM)
{
int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
}
}
#endif /* defined(LDM_PLATFORM)*/
/* Indicate that the SGX clocks are disabled */
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
#else /* !defined(NO_HARDWARE) */
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif /* !defined(NO_HARDWARE) */
}
/*!
******************************************************************************
@Function DisableSGXClocks
@Description Disable SGX clocks.
@Return none
******************************************************************************/
IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
/* SGX clocks already disabled? */
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
{
return;
}
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
#if !defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK)
omap_pm_set_min_bus_tput(&gpsPVRLDMDev->dev, OCP_INITIATOR_AGENT, 0);
#endif
SysDisableSGXInterrupts(psSysData);
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
{
int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
}
}
#if defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK)
{
struct gpu_platform_data *pdata;
int res;
pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data;
/*
* Request minimum frequency (list index 0) from DVFS layer if not already
* set. DVFS may report busy if early in initialization, but all other errors
* are considered serious. Upon any error we proceed assuming our safe frequency
* value to be in use as indicated by the "unknown" index.
*/
if (psSysSpecData->ui32SGXFreqListIndex != 0)
{
PVR_ASSERT(pdata->device_scale != IMG_NULL);
res = pdata->device_scale(&gpsPVRLDMDev->dev,
&gpsPVRLDMDev->dev,
psSysSpecData->pui32SGXFreqList[0]);
if (res == 0)
{
psSysSpecData->ui32SGXFreqListIndex = 0;
}
else if (res == -EBUSY)
{
PVR_DPF((PVR_DBG_WARNING, "DisableSGXClocks: Unable to scale SGX frequency (EBUSY)"));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
else if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: Unable to scale SGX frequency (%d)", res));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
}
}
#endif /* defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK) */
#endif /* defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) */
/* Indicate that the SGX clocks are disabled */
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
#else /* !defined(NO_HARDWARE) */
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif /* !defined(NO_HARDWARE) */
}
IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
{
return;
}
PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
SysDisableSGXInterrupts(psSysData);
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI)
{
int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res));
}
}
#if defined(SYS_OMAP4_HAS_DVFS_FRAMEWORK)
{
struct gpu_platform_data *pdata;
int res;
pdata = (struct gpu_platform_data *)gpsPVRLDMDev->dev.platform_data;
if (psSysSpecData->ui32SGXFreqListIndex != 0)
{
PVR_ASSERT(pdata->device_scale != IMG_NULL);
res = pdata->device_scale(&gpsPVRLDMDev->dev,
&gpsPVRLDMDev->dev,
psSysSpecData->pui32SGXFreqList[0]);
if (res == 0)
{
psSysSpecData->ui32SGXFreqListIndex = 0;
}
else if (res == -EBUSY)
{
PVR_DPF((PVR_DBG_WARNING, "DisableSGXClocks: Unable to scale SGX frequency (EBUSY)"));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
else if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: Unable to scale SGX frequency (%d)", res));
psSysSpecData->ui32SGXFreqListIndex = psSysSpecData->ui32SGXFreqListSize - 1;
}
}
}
#endif
#endif
atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
}
