static void write_tandy(Bitu port,Bitu val,Bitu iolen) { switch (port) { case 0x3d8: vga.tandy.mode_control=val; TandyCheckLineMask(); VGA_SetBlinking(val & 0x20); TANDY_FindMode(); break; case 0x3d9: write_color_select(val); break; case 0x3da: vga.tandy.reg_index=val; break; // case 0x3db: //Clear lightpen latch break; // case 0x3dc: //Preset lightpen latch break; // case 0x3dd: //Extended ram page address register: break; case 0x3de: write_tandy_reg(val); break; case 0x3df: vga.tandy.line_mask = val >> 6; vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7); vga.tandy.mem_bank = (val >> 3) & ((vga.tandy.line_mask&2) ? 0x6 : 0x7); TandyCheckLineMask(); VGA_SetupHandlers(); break; } }
static void write_tandy_reg(Bit8u val) { switch (vga.tandy.reg_index) { case 0x0: if (machine==MCH_PCJR) { vga.tandy.mode_control=val; VGA_SetBlinking(val & 0x20); PCJr_FindMode(); } else LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index); case 0x2: /* Border color */ vga.tandy.border_color=val; break; case 0x3: /* More control */ vga.tandy.gfx_control=val; if (machine==MCH_TANDY) TANDY_FindMode(); else PCJr_FindMode(); break; /* palette colors */ case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: VGA_ATTR_SetPalette(vga.tandy.reg_index-0x10,val & 0xf); break; default: LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index); } }
static void write_tandy_reg(Bit8u val) { switch (vga.tandy.reg_index) { case 0x0: if (machine==MCH_PCJR) { vga.tandy.mode_control=val; VGA_SetBlinking(val & 0x20); PCJr_FindMode(); } else { LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index); } break; case 0x2: /* Border color */ vga.tandy.border_color=val; break; case 0x3: /* More control */ vga.tandy.gfx_control=val; if (machine==MCH_TANDY) TANDY_FindMode(); else PCJr_FindMode(); break; case 0x5: /* Extended ram page register */ // Bit 0 enables extended ram // Bit 7 Switches clock, 0 -> cga 28.6 , 1 -> mono 32.5 vga.tandy.extended_ram = val; //This is a bit of a hack to enable mapping video memory differently for highres mode TandyCheckLineMask(); VGA_SetupHandlers(); break; case 0x8: /* Monitor mode seletion */ //Bit 1 select mode e, for 640x200x16, some double clocking thing? //Bit 4 select 350 line mode for hercules emulation LOG(LOG_VGAMISC,LOG_NORMAL)("Write %2X to tandy monitor mode",val ); break; /* palette colors */ case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: VGA_ATTR_SetPalette(vga.tandy.reg_index-0x10,val & 0xf); break; default: LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index); } }
static void write_tandy(Bitu port,Bitu val,Bitu iolen) { switch (port) { case 0x3d8: vga.tandy.mode_control=val; VGA_SetBlinking(val & 0x20); TANDY_FindMode(); break; case 0x3d9: write_color_select(val); break; case 0x3da: vga.tandy.reg_index=val; break; case 0x3de: write_tandy_reg(val); break; case 0x3df: vga.tandy.is_32k_mode=(val & 0x80)==0x80; vga.tandy.disp_bank=val & ((val & 0x80) ? 0x6 : 0x7); vga.tandy.mem_bank=(val >> 3) & ((val & 0x80) ? 0x6 : 0x7); VGA_SetupHandlers(); break; } }