void sp804_handler(int irq, void *pregs, void *pdata)
{
#if 0
printf("SP804 IRQ[%d]: T1 %x, T2: %x\n", irq, readl(TIMER1_VALUE(TIMER1_BASE)),
readl(TIMER2_VALUE(TIMER1_BASE)));
#endif
tickcount++;
//printf("tickcount: %d\n", tickcount);
writel(0x1, TIMER1_INTCLR(TIMER1_BASE));
}
/******************* Timer timeouts *************************/
static void via_t1_timeout (int which)
{
struct via6522 *v = via + which;
if (T1_CONTINUOUS (v->acr))
{
if (T1_SET_PB7(v->acr))
v->out_b ^= 0x80;
timer_reset (v->t1, V_CYCLES_TO_TIME(TIMER1_VALUE(v) + IFR_DELAY));
}
else
{
if (T1_SET_PB7(v->acr))
v->out_b |= 0x80;
v->t1 = 0;
v->time1=timer_get_time();
}
if (v->intf->out_b_func && v->ddr_b)
v->intf->out_b_func(0, v->out_b & v->ddr_b);
if (!(v->ifr & INT_T1))
via_set_int (v, INT_T1);
}
int via_read(int which, int offset)
{
struct via6522 *v = via + which;
int val = 0;
offset &= 0xf;
switch (offset)
{
case VIA_PB:
/* update the input */
if (PB_LATCH_ENABLE(v->acr) == 0)
if (v->intf->in_b_func) v->in_b = v->intf->in_b_func(0);
CLR_PB_INT(v);
/* combine input and output values, hold DDRB bit 7 high if T1_SET_PB7 */
if (T1_SET_PB7(v->acr))
val = (v->out_b & (v->ddr_b | 0x80)) | (v->in_b & ~(v->ddr_b | 0x80));
else
val = (v->out_b & v->ddr_b) + (v->in_b & ~v->ddr_b);
break;
case VIA_PA:
/* update the input */
if (PA_LATCH_ENABLE(v->acr) == 0)
if (v->intf->in_a_func) v->in_a = v->intf->in_a_func(0);
/* combine input and output values */
val = (v->out_a & v->ddr_a) + (v->in_a & ~v->ddr_a);
CLR_PA_INT(v);
/* If CA2 is configured as output and in pulse or handshake mode,
CA2 is set now */
if (CA2_AUTO_HS(v->pcr))
{
if (v->out_ca2)
{
/* set CA2 */
v->out_ca2 = 0;
/* call the CA2 output function */
if (v->intf->out_ca2_func) v->intf->out_ca2_func(0, 0);
}
}
break;
case VIA_PANH:
/* update the input */
if (PA_LATCH_ENABLE(v->acr) == 0)
if (v->intf->in_a_func) v->in_a = v->intf->in_a_func(0);
/* combine input and output values */
val = (v->out_a & v->ddr_a) + (v->in_a & ~v->ddr_a);
break;
case VIA_DDRB:
val = v->ddr_b;
break;
case VIA_DDRA:
val = v->ddr_a;
break;
case VIA_T1CL:
via_clear_int (v, INT_T1);
if (v->t1)
val = V_TIME_TO_CYCLES(timer_timeleft(v->t1)) & 0xff;
else
{
if ( T1_CONTINUOUS(v->acr) )
{
val = (TIMER1_VALUE(v)-
(V_TIME_TO_CYCLES(timer_get_time()-v->time1)
%TIMER1_VALUE(v))-1)&0xff;
}
else
{
val = (0x10000-
(V_TIME_TO_CYCLES(timer_get_time()-v->time1)&0xffff)
-1)&0xff;
}
}
break;
case VIA_T1CH:
if (v->t1)
val = V_TIME_TO_CYCLES(timer_timeleft(v->t1)) >> 8;
else
{
if ( T1_CONTINUOUS(v->acr) )
{
val = (TIMER1_VALUE(v)-
(V_TIME_TO_CYCLES(timer_get_time()-v->time1)
%TIMER1_VALUE(v))-1)>>8;
}
else
{
