unsigned long wiz_timer_read( void )
{
unsigned int microsec;
TIMER_REG(0x08) = 0x4b; /* run timer, latch value */
microsec = TIMER_REG(0);
return (microsec/1000);
}
uint16_t hwtimer_read(int num)
{
uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
/* somehow a read results in an abort */
if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
return 0xFFFF;
return getreg16(TIMER_REG(num, READ_TIMER));
}
void wiz_timer_close( void )
{
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x23;
TIMER_REG(0x00) = 0;
TIMER_REG(0x40) = 0;
TIMER_REG(0x44) = 0;
munmap((void *)memregs32, 0x20000);
close(wiz_dev_mem);
printf( "WIZ: hardware timer closed\n" );
}
void hwtimer_enable(int num, int on)
{
uint8_t ctl;
if (num < 1 || num > 2) {
printf("Unknown timer %u\n", num);
return;
}
ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
if (on)
ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
else
ctl &= ~CNTL_START;
putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
}
void wiz_timer_init( void )
{
/* open /dev/mem to access registers */
wiz_dev_mem = open("/dev/mem", O_RDWR);
if(wiz_dev_mem < 0) {
fprintf(stderr, "WIZ: Unable to open /dev/mem");
}
/* get access to the registers */
memregs32 = (volatile unsigned int *)mmap(0, 0x20000, PROT_READ|PROT_WRITE, MAP_SHARED, wiz_dev_mem, 0xC0000000);
if(memregs32 == (volatile unsigned int *)0xFFFFFFFF) {
fprintf(stderr, "WIZ: Could not mmap hardware registers\n");
}
TIMER_REG(0x44) = 0x922;
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x6b;
}
void a_hw__init(void)
{
#if A_PLATFORM_GP2X
if(a_file_exists("./mmuhack.o")) {
system("/sbin/rmmod mmuhack");
system("/sbin/insmod mmuhack.o");
int mmufd = open("/dev/mmuhack", O_RDWR);
if(mmufd >= 0) {
close(mmufd);
g_mmuHackOn = 1;
}
}
if(a_settings_getInt("app.mhz") > 0) {
setCpuSpeed(a_settings_getInt("app.mhz"));
}
setRamTimings(6, 4, 1, 1, 1, 2, 2);
#elif A_PLATFORM_WIZ
if(a_file_exists("./mmuhack.ko")) {
system("/sbin/rmmod mmuhack");
system("/sbin/insmod mmuhack.ko");
int mmufd = open("/dev/mmuhack", O_RDWR);
if(mmufd >= 0) {
close(mmufd);
g_mmuHackOn = 1;
}
}
#endif
#if A_PLATFORM_WIZ || A_PLATFORM_CAANOO
g_memfd = open("/dev/mem", O_RDWR);
g_memregs = mmap(0, 0x20000, PROT_READ | PROT_WRITE, MAP_SHARED, g_memfd, 0xc0000000);
TIMER_REG(0x44) = 0x922;
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x6b;
#endif
}
void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
{
uint8_t ctl;
ctl = (pre_scale & 0x7) << 2;
if (auto_reload)
ctl |= CNTL_AUTO_RELOAD;
putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
}
void GW_PlatformWIZ::custom_finalize()
{
if(m_MEM>=0)
{
if (MEMREGS32!=MAP_FAILED)
{
/* stop timer */
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x23;
TIMER_REG(0x00) = 0;
TIMER_REG(0x40) = 0;
TIMER_REG(0x44) = 0;
}
close(m_MEM);
m_MEM = -1;
MEMREGS16 = (uint16_t*)MAP_FAILED;
MEMREGS32 = (uint32_t*)MAP_FAILED;
}
}
/**
* \b archUsleep
*
* Simple spin loop of at least the specified microseconds.
*
* @param[in] microsecs Number of microseconds to sleep
*
* @return None
*
*/
void archUsleep (int32_t microsecs)
{
int32_t start_time, delay_timer_ticks;
/* Check we are initialised */
if (initialised == FALSE)
{
timer_init();
}
/* Get the current 24MHz count */
start_time = TIMER_REG(DM36X_TIMER_TIM12);
/* Translate delay in usecs to delay in 24MHz ticks */
delay_timer_ticks = ((TIMER_CLK / 1000000) * microsecs);
/* Wait in a spin-loop for timer to expire */
while (((int32_t)TIMER_REG(DM36X_TIMER_TIM12) - start_time) < delay_timer_ticks)
;
}
/**
* \b archUsecStart
*
* Start a usec timer session for use with archUsecDiff() layer.
*
* @retval Start time for use in subsequent archUsecDiff() calls
*
*/
int32_t archUsecStart (void)
{
/* Check we are initialised */
if (initialised == FALSE)
{
timer_init();
}
/* Return the current 24MHz count */
return (TIMER_REG(DM36X_TIMER_TIM12));
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
enter_critical_section();
t_callback = callback;
callback_arg = arg;
tick_interval = interval;
uint32_t ticks_per_interval = (uint64_t)interval * TIMER_TICK_RATE / 1000; // interval is in ms
TIMER_REG(TCLR) = 0; // stop the timer
TIMER_REG(TLDR) = -ticks_per_interval;
TIMER_REG(TTGR) = 1;
TIMER_REG(TIER) = 0x2;
TIMER_REG(TCLR) = 0x3; // autoreload, start
unmask_interrupt(GPT2_IRQ);
exit_critical_section();
return NO_ERROR;
}
/**
* \b archUsleepCheckExpired
*
* Test whether a usleep timer session has expired.
*
* @param[in] start_time Beginning of timer expiry check session (returned by archUsleepStart())
* @param[in] delay_usecs Number of microsecs to check have expired after start_timE
*
* @retval 1=Timer expired, 0=Not expired
*
*/
int archUsleepCheckExpired (int32_t start_time, int32_t delay_usecs)
{
int32_t delay_timer_ticks;
int status;
/* Translate delay in usecs to delay in 24MHz ticks */
delay_timer_ticks = ((TIMER_CLK / 1000000) * delay_usecs);
/* Check if timer has expired */
status = (((int32_t)TIMER_REG(DM36X_TIMER_TIM12) - start_time) < delay_timer_ticks) ? 0 : 1;
return (status);
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
spin_lock_saved_state_t statep;
arch_interrupt_save(&statep, SPIN_LOCK_FLAG_IRQ);
t_callback = callback;
callback_arg = arg;
tick_interval = interval;
uint32_t ticks_per_interval = (uint64_t)interval * TIMER_TICK_RATE / 1000; // interval is in ms
TIMER_REG(TCLR) = 0; // stop the timer
TIMER_REG(TLDR) = -ticks_per_interval;
TIMER_REG(TTGR) = 1;
TIMER_REG(TIER) = 0x2;
TIMER_REG(TCLR) = 0x3; // autoreload, start
unmask_interrupt(GPT2_IRQ);
arch_interrupt_restore(statep, SPIN_LOCK_FLAG_IRQ);
return NO_ERROR;
}
void GW_PlatformWIZ::custom_initialize()
{
SDL_Joystick *joystick = SDL_JoystickOpen(0); // initialize the joystick and buttons. Number '0' is the only one.
if (!joystick) // should not happen
throw GW_Exception(string("Unable to open joystick: "+string(SDL_GetError())));
m_MEM = open("/dev/mem", O_RDWR );
if (m_MEM<0)
throw GW_Exception(string("/dev/mem open failed."));
MEMREGS32 = (volatile uint32_t*)mmap(0,MEM_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, m_MEM, MEM_BASE);
if (MEMREGS32==MAP_FAILED)
throw GW_Exception(string("mmap failed."));
MEMREGS16 = (volatile uint16_t*)MEMREGS32;
/* start timer */
TIMER_REG(0x44) = 0x922;
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x6b;
}
void a_hw__uninit(void)
{
#if A_PLATFORM_WIZ || A_PLATFORM_CAANOO
TIMER_REG(0x40) = 0x0c;
TIMER_REG(0x08) = 0x23;
TIMER_REG(0x00) = 0;
TIMER_REG(0x40) = 0;
TIMER_REG(0x44) = 0;
close(g_memfd);
#endif
#if A_PLATFORM_GP2X || A_PLATFORM_WIZ
if(g_mmuHackOn) {
system("/sbin/rmmod mmuhack");
}
#endif
#if A_PLATFORM_GP2X
setRamTimings(8, 16, 3, 8, 8, 8, 8);
#endif
}
void platform_init_timer(void)
{
/* GPT2 */
RMWREG32(CM_CLKSEL_PER, 0, 1, 1);
RMWREG32(CM_ICLKEN_PER, 3, 1, 1);
RMWREG32(CM_FCLKEN_PER, 3, 1, 1);
// reset the GP timer
TIMER_REG(TIOCP_CFG) = 0x2;
while ((TIMER_REG(TISTAT) & 1) == 0)
;
// set GPT2-9 clock inputs over to 32k
*REG32(CM_CLKSEL_PER) = 0;
// disable ints
TIMER_REG(TIER) = 0;
TIMER_REG(TISR) = 0x7; // clear any pending bits
// XXX make sure 32K timer is running
register_int_handler(GPT2_IRQ, &os_timer_tick, NULL);
}
/**
* \b timer_init
*
* Initialisation of TIMER1 hardware.
*
* @retval ATOM_OK Success
* @retval ATOM_ERROR Failed
*/
static int timer_init (void)
{
int status;
/* Check we are not already initialised */
if (initialised == FALSE)
{
/* Initialise TIMER1 registers for free-running high-speed 24MHz timer */
/* Reset & disable all TIMER1 timers */
TIMER_REG(DM36X_TIMER_INTCTL_STAT) = 0; /* Disable interrupts */
TIMER_REG(DM36X_TIMER_TCR) = 0; /* Disable all TIMER1 timers */
TIMER_REG(DM36X_TIMER_TGCR) = 0; /* Put all TIMER1 timers in reset */
TIMER_REG(DM36X_TIMER_TIM12) = 0; /* Clear Timer 1:2 */
/* Set up Timer 1:2 in 32-bit unchained mode */
TIMER_REG(DM36X_TIMER_TGCR) = (1 << 2); /* Select 32-bit unchained mode (TIMMODE) */
TIMER_REG(DM36X_TIMER_TGCR) |= (1 << 0); /* Remove Timer 1:2 from reset (TIM12RS) */
TIMER_REG(DM36X_TIMER_PRD12) = ~0; /* Set period to free-running 24MHz clock (PRD12) */
TIMER_REG(DM36X_TIMER_TCR) |= (0 << 8); /* Select external clock source for Timer 1:2 (CLKSRC12) */
/* Enable timer */
TIMER_REG(DM36X_TIMER_TCR) |= (2 << 6); /* Enable Timer 1:2 continuous (ENAMODE12) */
/* Success */
initialised = TRUE;
status = ATOM_OK;
}
/* Already initialised */
else
{
/* Success */
status = ATOM_OK;
}
/* Finished */
return (status);
}
static enum handler_return os_timer_tick(void *arg)
{
TIMER_REG(TISR) = TIMER_REG(TISR);
return t_callback(callback_arg, current_time());
}
void platform_halt_timers(void)
{
TIMER_REG(TCLR) = 0;
}
/**
* \b archUsecDiff
*
* Calculate the usecs that have expired since the passed "start_time".
*
* The 24MHz timer rolls over every 178 seconds. The use of a signed
* integer means that this cannot be used to measure periods over 89 seconds.
*
* @param[in] start_time Beginning of time difference session (returned by archUsecStart())
*
* @retval Number of microseconds expired since start_time
*
*/
int32_t archUsecDiff (int32_t start_time)
{
/* Translate diff in 24MHz ticks to usecs */
return (((int32_t)TIMER_REG(DM36X_TIMER_TIM12) - start_time) / (TIMER_CLK / 1000000));
}
uint32_t a_hw__getMs(void)
{
TIMER_REG(0x08) = 0x4b; // run timer, latch value
return TIMER_REG(0) / 1000;
}
unsigned int GW_PlatformWIZ::time_ms_get()
{
TIMER_REG(0x08) = 0x4b; /* run timer, latch value */
return TIMER_REG(0) / 1000; //timer is us
}
void hwtimer_load(int num, uint16_t val)
{
putreg16(val, TIMER_REG(num, LOAD_TIMER));
}
