void TSI_Init (void)
{
SIM_SCGC5 |= SIM_SCGC5_TSI_MASK; // Enable clock gating for TSI
/* Enable proper GPIO as TSI channels */
PORTB_PCR17 = PORT_PCR_MUX(0); // PTA1 as TSI channel 2
PORTB_PCR16 = PORT_PCR_MUX(0); // PTA2 as TSI channel 3
enable_irq(TSI_irq_no);
TSI0_GENCS |= (TSI_GENCS_ESOR_MASK
| TSI_GENCS_MODE(0)
| TSI_GENCS_REFCHRG(4)
| TSI_GENCS_DVOLT(0)
| TSI_GENCS_EXTCHRG(7)
| TSI_GENCS_PS(4)
| TSI_GENCS_NSCN(11)
| TSI_GENCS_TSIIEN_MASK
| TSI_GENCS_STPE_MASK
//| TSI_GENCS_STM_MASK //Trigger for the module 0=Sofware
);
TSI0_GENCS |= TSI_GENCS_TSIEN_MASK;
TSI_SelfCalibration();
}
/*******************************************************************
* TSI module initialization.
*/
void TSI_Init (void)
{
SIM_SCGC5 |= SIM_SCGC5_TSI_MASK; // Enable clock gating for TSI
/* Enable proper GPIO as TSI channels */
PORTA_PCR13 = PORT_PCR_MUX(0); // PTB16 as TSI channel 9
PORTB_PCR12 = PORT_PCR_MUX(0); // PTB17 as TSI channel 8
enable_irq(INT_TSI0-16);
TSI0_GENCS |= (TSI_GENCS_ESOR_MASK
| TSI_GENCS_MODE(0)
| TSI_GENCS_REFCHRG(4)
| TSI_GENCS_DVOLT(0)
| TSI_GENCS_EXTCHRG(7)
| TSI_GENCS_PS(4)
| TSI_GENCS_NSCN(11)
| TSI_GENCS_TSIIEN_MASK
| TSI_GENCS_STPE_MASK
//| TSI_GENCS_STM_MASK //Trigger for the module 0=Sofware
);
TSI0_GENCS |= TSI_GENCS_TSIEN_MASK; //Enable TSI module.
TSI_SelfCalibration();
}
