static void
tws_dmamap_data_load_cbfn(void *arg, bus_dma_segment_t *segs,
int nseg, int error)
{
struct tws_request *req = (struct tws_request *)arg;
struct tws_softc *sc = req->sc;
u_int16_t sgls = nseg;
void *sgl_ptr;
struct tws_cmd_generic *gcmd;
if ( error ) {
TWS_TRACE(sc, "SOMETHING BAD HAPPENED! error = %d\n", error, 0);
}
if ( error == EFBIG ) {
TWS_TRACE(sc, "not enough data segs", 0, nseg);
req->error_code = error;
req->ccb_ptr->ccb_h.status = CAM_REQ_TOO_BIG;
return;
}
if ( req->flags & TWS_DIR_IN )
bus_dmamap_sync(req->sc->data_tag, req->dma_map,
BUS_DMASYNC_PREREAD);
if ( req->flags & TWS_DIR_OUT )
bus_dmamap_sync(req->sc->data_tag, req->dma_map,
BUS_DMASYNC_PREWRITE);
if ( segs ) {
if ( (req->type == TWS_REQ_TYPE_PASSTHRU &&
GET_OPCODE(req->cmd_pkt->cmd.pkt_a.res__opcode) !=
TWS_FW_CMD_EXECUTE_SCSI) ||
req->type == TWS_REQ_TYPE_GETSET_PARAM) {
gcmd = &req->cmd_pkt->cmd.pkt_g.generic;
sgl_ptr = (u_int32_t *)(gcmd) + gcmd->size;
gcmd->size += sgls *
((req->sc->is64bit && !tws_use_32bit_sgls) ? 4 : 2 );
tws_fill_sg_list(req->sc, (void *)segs, sgl_ptr, sgls);
} else {
tws_fill_sg_list(req->sc, (void *)segs,
(void *)&(req->cmd_pkt->cmd.pkt_a.sg_list), sgls);
req->cmd_pkt->cmd.pkt_a.lun_h4__sgl_entries |= sgls ;
}
}
req->error_code = tws_submit_command(req->sc, req);
}
static void
tws_fill_sg_list(struct tws_softc *sc, void *sgl_src, void *sgl_dest,
u_int16_t num_sgl_entries)
{
int i;
if ( sc->is64bit ) {
struct tws_sg_desc64 *sgl_s = (struct tws_sg_desc64 *)sgl_src;
if ( !tws_use_32bit_sgls ) {
struct tws_sg_desc64 *sgl_d = (struct tws_sg_desc64 *)sgl_dest;
if ( num_sgl_entries > TWS_MAX_64BIT_SG_ELEMENTS )
TWS_TRACE(sc, "64bit sg overflow", num_sgl_entries, 0);
for (i = 0; i < num_sgl_entries; i++) {
sgl_d[i].address = sgl_s->address;
sgl_d[i].length = sgl_s->length;
sgl_d[i].flag = 0;
sgl_d[i].reserved = 0;
sgl_s = (struct tws_sg_desc64 *) (((u_int8_t *)sgl_s) +
sizeof(bus_dma_segment_t));
}
} else {
struct tws_sg_desc32 *sgl_d = (struct tws_sg_desc32 *)sgl_dest;
if ( num_sgl_entries > TWS_MAX_32BIT_SG_ELEMENTS )
TWS_TRACE(sc, "32bit sg overflow", num_sgl_entries, 0);
for (i = 0; i < num_sgl_entries; i++) {
sgl_d[i].address = sgl_s->address;
sgl_d[i].length = sgl_s->length;
sgl_d[i].flag = 0;
sgl_s = (struct tws_sg_desc64 *) (((u_int8_t *)sgl_s) +
sizeof(bus_dma_segment_t));
}
}
} else {
struct tws_sg_desc32 *sgl_s = (struct tws_sg_desc32 *)sgl_src;
struct tws_sg_desc32 *sgl_d = (struct tws_sg_desc32 *)sgl_dest;
if ( num_sgl_entries > TWS_MAX_32BIT_SG_ELEMENTS )
TWS_TRACE(sc, "32bit sg overflow", num_sgl_entries, 0);
for (i = 0; i < num_sgl_entries; i++) {
sgl_d[i].address = sgl_s[i].address;
sgl_d[i].length = sgl_s[i].length;
sgl_d[i].flag = 0;
}
}
}
int32_t
tws_map_request(struct tws_softc *sc, struct tws_request *req)
{
int32_t error = 0;
/* If the command involves data, map that too. */
if (req->data != NULL) {
/*
* Map the data buffer into bus space and build the SG list.
*/
lockmgr(&sc->io_lock, LK_EXCLUSIVE);
error = bus_dmamap_load(sc->data_tag, req->dma_map,
req->data, req->length,
tws_dmamap_data_load_cbfn, req,
BUS_DMA_WAITOK);
lockmgr(&sc->io_lock, LK_RELEASE);
if (error == EINPROGRESS) {
TWS_TRACE(sc, "in progress", 0, error);
/* tws_freeze_simq(sc); */
error = TWS_REQ_ERR_INPROGRESS;
}
} else { /* no data involved */
error = tws_submit_command(sc, req);
}
req->error_code = error;
return(error);
}
static void
tws_intr_attn_error(struct tws_softc *sc)
{
u_int32_t db=0;
TWS_TRACE(sc, "attn error", 0, 0);
tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
db = tws_read_reg(sc, TWS_I2O0_IOBDB, 4);
device_printf(sc->tws_dev, "Micro controller error.\n");
tws_reset(sc);
}
static int
tws_setup_irq(struct tws_softc *sc)
{
int messages;
u_int16_t cmd;
cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
switch(sc->intr_type) {
case TWS_INTx :
cmd = cmd & ~0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 0;
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
if ( ! sc->irq_res[0] )
return(FAILURE);
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
return(FAILURE);
device_printf(sc->tws_dev, "Using legacy INTx\n");
break;
case TWS_MSI :
cmd = cmd | 0x0400;
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
sc->irqs = 1;
sc->irq_res_id[0] = 1;
messages = 1;
if (pci_alloc_msi(sc->tws_dev, &messages) != 0 ) {
TWS_TRACE(sc, "pci alloc msi fail", 0, messages);
return(FAILURE);
}
sc->irq_res[0] = bus_alloc_resource_any(sc->tws_dev, SYS_RES_IRQ,
&sc->irq_res_id[0], RF_SHAREABLE | RF_ACTIVE);
if ( !sc->irq_res[0] )
return(FAILURE);
if ( tws_setup_intr(sc, sc->irqs) == FAILURE )
return(FAILURE);
device_printf(sc->tws_dev, "Using MSI\n");
break;
}
return(SUCCESS);
}
int32_t
tws_map_request(struct tws_softc *sc, struct tws_request *req)
{
int32_t error = 0;
/* If the command involves data, map that too. */
if (req->data != NULL) {
int my_flags = ((req->type == TWS_REQ_TYPE_SCSI_IO) ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
/*
* Map the data buffer into bus space and build the SG list.
*/
mtx_lock(&sc->io_lock);
if (req->flags & TWS_DATA_CCB)
error = bus_dmamap_load_ccb(sc->data_tag, req->dma_map,
req->data,
tws_dmamap_data_load_cbfn, req,
my_flags);
else
error = bus_dmamap_load(sc->data_tag, req->dma_map,
req->data, req->length,
tws_dmamap_data_load_cbfn, req,
my_flags);
mtx_unlock(&sc->io_lock);
if (error == EINPROGRESS) {
TWS_TRACE(sc, "in progress", 0, error);
tws_freeze_simq(sc, req);
error = 0; // EINPROGRESS is not a fatal error.
}
} else { /* no data involved */
error = tws_submit_command(sc, req);
}
return(error);
}
int
tws_init_connect(struct tws_softc *sc, u_int16_t mcreadits )
{
struct tws_request *req;
struct tws_cmd_init_connect *initc;
u_int16_t reqid;
u_int64_t mfa;
TWS_TRACE_DEBUG(sc, "entry", 0, mcreadits);
#if 0
req = tws_get_request(sc, TWS_REQ_TYPE_INTERNAL_CMD);
#else // 0
req = &sc->reqs[TWS_REQ_TYPE_INTERNAL_CMD];
bzero(&req->cmd_pkt->cmd, sizeof(struct tws_command_apache));
req->data = NULL;
req->length = 0;
req->type = TWS_REQ_TYPE_INTERNAL_CMD;
req->flags = TWS_DIR_UNKNOWN;
req->error_code = TWS_REQ_RET_INVALID;
req->cb = NULL;
req->ccb_ptr = NULL;
req->thandle.callout = NULL;
req->next = req->prev = NULL;
req->state = TWS_REQ_STATE_BUSY;
#endif // 0
if ( req == NULL ) {
TWS_TRACE_DEBUG(sc, "no requests", 0, 0);
// device_printf(sc->tws_dev, "No requests for initConnect\n");
return(FAILURE);
}
tws_swap16(0xbeef); /* just for test */
tws_swap32(0xdeadbeef); /* just for test */
tws_swap64(0xdeadbeef); /* just for test */
initc = &(req->cmd_pkt->cmd.pkt_g.init_connect);
/* req->cmd_pkt->hdr.header_desc.size_header = 128; */
initc->res1__opcode =
BUILD_RES__OPCODE(0, TWS_FW_CMD_INIT_CONNECTION);
initc->size = 6;
initc->request_id = req->request_id;
initc->message_credits = mcreadits;
initc->features |= TWS_BIT_EXTEND;
if ( sc->is64bit && !tws_use_32bit_sgls )
initc->features |= TWS_64BIT_SG_ADDRESSES;
/* assuming set features is always on */
initc->size = 6;
initc->fw_srl = sc->cinfo.working_srl = TWS_CURRENT_FW_SRL;
initc->fw_arch_id = 0;
initc->fw_branch = sc->cinfo.working_branch = 0;
initc->fw_build = sc->cinfo.working_build = 0;
req->error_code = tws_submit_command(sc, req);
reqid = tws_poll4_response(sc, &mfa);
if ( reqid != TWS_INVALID_REQID && reqid == req->request_id ) {
sc->cinfo.fw_on_ctlr_srl = initc->fw_srl;
sc->cinfo.fw_on_ctlr_branch = initc->fw_branch;
sc->cinfo.fw_on_ctlr_build = initc->fw_build;
sc->stats.reqs_out++;
req->state = TWS_REQ_STATE_FREE;
}
else {
/*
* REVISIT::If init connect fails we need to reset the ctlr
* and try again?
*/
TWS_TRACE(sc, "unexpected req_id ", reqid, 0);
TWS_TRACE(sc, "INITCONNECT FAILED", reqid, 0);
return(FAILURE);
}
return(SUCCESS);
}
static int
tws_detach(device_t dev)
{
struct tws_softc *sc = device_get_softc(dev);
int i;
u_int32_t reg;
TWS_TRACE_DEBUG(sc, "entry", 0, 0);
mtx_lock(&sc->gen_lock);
tws_send_event(sc, TWS_UNINIT_START);
mtx_unlock(&sc->gen_lock);
/* needs to disable interrupt before detaching from cam */
tws_turn_off_interrupts(sc);
/* clear door bell */
tws_write_reg(sc, TWS_I2O0_HOBDBC, ~0, 4);
reg = tws_read_reg(sc, TWS_I2O0_HIMASK, 4);
TWS_TRACE_DEBUG(sc, "turn-off-intr", reg, 0);
sc->obfl_q_overrun = false;
tws_init_connect(sc, 1);
/* Teardown the state in our softc created in our attach routine. */
/* Disconnect the interrupt handler. */
tws_teardown_intr(sc);
/* Release irq resource */
for(i=0;i<sc->irqs;i++) {
if ( sc->irq_res[i] ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
TWS_TRACE(sc, "bus release irq resource",
i, sc->irq_res_id[i]);
}
}
if ( sc->intr_type == TWS_MSI ) {
pci_release_msi(sc->tws_dev);
}
tws_cam_detach(sc);
/* Release memory resource */
if ( sc->mfa_res ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
TWS_TRACE(sc, "bus release mem resource", 0, sc->mfa_res_id);
}
if ( sc->reg_res ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
TWS_TRACE(sc, "bus release mem resource", 0, sc->reg_res_id);
}
free(sc->reqs, M_TWS);
free(sc->sense_bufs, M_TWS);
free(sc->scan_ccb, M_TWS);
if (sc->ioctl_data_mem)
bus_dmamem_free(sc->data_tag, sc->ioctl_data_mem, sc->ioctl_data_map);
free(sc->aen_q.q, M_TWS);
free(sc->trace_q.q, M_TWS);
mtx_destroy(&sc->q_lock);
mtx_destroy(&sc->sim_lock);
mtx_destroy(&sc->gen_lock);
mtx_destroy(&sc->io_lock);
destroy_dev(sc->tws_cdev);
sysctl_ctx_free(&sc->tws_clist);
return (0);
}
static int
tws_attach(device_t dev)
{
struct tws_softc *sc = device_get_softc(dev);
u_int32_t bar;
int error=0,i;
/* no tracing yet */
/* Look up our softc and initialize its fields. */
sc->tws_dev = dev;
sc->device_id = pci_get_device(dev);
sc->subvendor_id = pci_get_subvendor(dev);
sc->subdevice_id = pci_get_subdevice(dev);
/* Intialize mutexes */
mtx_init( &sc->q_lock, "tws_q_lock", NULL, MTX_DEF);
mtx_init( &sc->sim_lock, "tws_sim_lock", NULL, MTX_DEF);
mtx_init( &sc->gen_lock, "tws_gen_lock", NULL, MTX_DEF);
mtx_init( &sc->io_lock, "tws_io_lock", NULL, MTX_DEF | MTX_RECURSE);
if ( tws_init_trace_q(sc) == FAILURE )
printf("trace init failure\n");
/* send init event */
mtx_lock(&sc->gen_lock);
tws_send_event(sc, TWS_INIT_START);
mtx_unlock(&sc->gen_lock);
#if _BYTE_ORDER == _BIG_ENDIAN
TWS_TRACE(sc, "BIG endian", 0, 0);
#endif
/* sysctl context setup */
sysctl_ctx_init(&sc->tws_clist);
sc->tws_oidp = SYSCTL_ADD_NODE(&sc->tws_clist,
SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
device_get_nameunit(dev),
CTLFLAG_RD, 0, "");
if ( sc->tws_oidp == NULL ) {
tws_log(sc, SYSCTL_TREE_NODE_ADD);
goto attach_fail_1;
}
SYSCTL_ADD_STRING(&sc->tws_clist, SYSCTL_CHILDREN(sc->tws_oidp),
OID_AUTO, "driver_version", CTLFLAG_RD,
TWS_DRIVER_VERSION_STRING, 0, "TWS driver version");
pci_enable_busmaster(dev);
bar = pci_read_config(dev, TWS_PCI_BAR0, 4);
TWS_TRACE_DEBUG(sc, "bar0 ", bar, 0);
bar = pci_read_config(dev, TWS_PCI_BAR1, 4);
bar = bar & ~TWS_BIT2;
TWS_TRACE_DEBUG(sc, "bar1 ", bar, 0);
/* MFA base address is BAR2 register used for
* push mode. Firmware will evatualy move to
* pull mode during witch this needs to change
*/
#ifndef TWS_PULL_MODE_ENABLE
sc->mfa_base = (u_int64_t)pci_read_config(dev, TWS_PCI_BAR2, 4);
sc->mfa_base = sc->mfa_base & ~TWS_BIT2;
TWS_TRACE_DEBUG(sc, "bar2 ", sc->mfa_base, 0);
#endif
/* allocate MMIO register space */
sc->reg_res_id = TWS_PCI_BAR1; /* BAR1 offset */
if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
&(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE))
== NULL) {
tws_log(sc, ALLOC_MEMORY_RES);
goto attach_fail_1;
}
sc->bus_tag = rman_get_bustag(sc->reg_res);
sc->bus_handle = rman_get_bushandle(sc->reg_res);
#ifndef TWS_PULL_MODE_ENABLE
/* Allocate bus space for inbound mfa */
sc->mfa_res_id = TWS_PCI_BAR2; /* BAR2 offset */
if ((sc->mfa_res = bus_alloc_resource(dev, SYS_RES_MEMORY,
&(sc->mfa_res_id), 0, ~0, 0x100000, RF_ACTIVE))
== NULL) {
tws_log(sc, ALLOC_MEMORY_RES);
goto attach_fail_2;
}
sc->bus_mfa_tag = rman_get_bustag(sc->mfa_res);
sc->bus_mfa_handle = rman_get_bushandle(sc->mfa_res);
#endif
/* Allocate and register our interrupt. */
sc->intr_type = TWS_INTx; /* default */
if ( tws_enable_msi )
sc->intr_type = TWS_MSI;
if ( tws_setup_irq(sc) == FAILURE ) {
tws_log(sc, ALLOC_MEMORY_RES);
goto attach_fail_3;
}
/*
* Create a /dev entry for this device. The kernel will assign us
* a major number automatically. We use the unit number of this
* device as the minor number and name the character device
* "tws<unit>".
*/
sc->tws_cdev = make_dev(&tws_cdevsw, device_get_unit(dev),
UID_ROOT, GID_OPERATOR, S_IRUSR | S_IWUSR, "tws%u",
device_get_unit(dev));
sc->tws_cdev->si_drv1 = sc;
if ( tws_init(sc) == FAILURE ) {
tws_log(sc, TWS_INIT_FAILURE);
goto attach_fail_4;
}
if ( tws_init_ctlr(sc) == FAILURE ) {
tws_log(sc, TWS_CTLR_INIT_FAILURE);
goto attach_fail_4;
}
if ((error = tws_cam_attach(sc))) {
tws_log(sc, TWS_CAM_ATTACH);
goto attach_fail_4;
}
/* send init complete event */
mtx_lock(&sc->gen_lock);
tws_send_event(sc, TWS_INIT_COMPLETE);
mtx_unlock(&sc->gen_lock);
TWS_TRACE_DEBUG(sc, "attached successfully", 0, sc->device_id);
return(0);
attach_fail_4:
tws_teardown_intr(sc);
destroy_dev(sc->tws_cdev);
attach_fail_3:
for(i=0;i<sc->irqs;i++) {
if ( sc->irq_res[i] ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_IRQ, sc->irq_res_id[i], sc->irq_res[i]))
TWS_TRACE(sc, "bus irq res", 0, 0);
}
}
#ifndef TWS_PULL_MODE_ENABLE
attach_fail_2:
#endif
if ( sc->mfa_res ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_MEMORY, sc->mfa_res_id, sc->mfa_res))
TWS_TRACE(sc, "bus release ", 0, sc->mfa_res_id);
}
if ( sc->reg_res ){
if (bus_release_resource(sc->tws_dev,
SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res))
TWS_TRACE(sc, "bus release2 ", 0, sc->reg_res_id);
}
attach_fail_1:
mtx_destroy(&sc->q_lock);
mtx_destroy(&sc->sim_lock);
mtx_destroy(&sc->gen_lock);
mtx_destroy(&sc->io_lock);
sysctl_ctx_free(&sc->tws_clist);
return (ENXIO);
}
static int32_t
tws_execute_scsi(struct tws_softc *sc, union ccb *ccb)
{
struct tws_command_packet *cmd_pkt;
struct tws_request *req;
struct ccb_hdr *ccb_h = &(ccb->ccb_h);
struct ccb_scsiio *csio = &(ccb->csio);
int error;
u_int16_t lun;
mtx_assert(&sc->sim_lock, MA_OWNED);
if (ccb_h->target_id >= TWS_MAX_NUM_UNITS) {
TWS_TRACE_DEBUG(sc, "traget id too big", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status |= CAM_TID_INVALID;
xpt_done(ccb);
return(0);
}
if (ccb_h->target_lun >= TWS_MAX_NUM_LUNS) {
TWS_TRACE_DEBUG(sc, "target lun 2 big", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status |= CAM_LUN_INVALID;
xpt_done(ccb);
return(0);
}
if(ccb_h->flags & CAM_CDB_PHYS) {
TWS_TRACE_DEBUG(sc, "cdb phy", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status = CAM_REQ_INVALID;
xpt_done(ccb);
return(0);
}
/*
* We are going to work on this request. Mark it as enqueued (though
* we don't actually queue it...)
*/
ccb_h->status |= CAM_SIM_QUEUED;
req = tws_get_request(sc, TWS_REQ_TYPE_SCSI_IO);
if ( !req ) {
TWS_TRACE_DEBUG(sc, "no reqs", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status |= CAM_REQUEUE_REQ;
xpt_done(ccb);
return(0);
}
if((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
if(ccb_h->flags & CAM_DIR_IN)
req->flags |= TWS_DIR_IN;
if(ccb_h->flags & CAM_DIR_OUT)
req->flags |= TWS_DIR_OUT;
} else {
req->flags = TWS_DIR_NONE; /* no data */
}
req->type = TWS_REQ_TYPE_SCSI_IO;
req->cb = tws_scsi_complete;
cmd_pkt = req->cmd_pkt;
/* cmd_pkt->hdr.header_desc.size_header = 128; */
cmd_pkt->cmd.pkt_a.res__opcode = TWS_FW_CMD_EXECUTE_SCSI;
cmd_pkt->cmd.pkt_a.unit = ccb_h->target_id;
cmd_pkt->cmd.pkt_a.status = 0;
cmd_pkt->cmd.pkt_a.sgl_offset = 16;
/* lower nibble */
lun = ccb_h->target_lun & 0XF;
lun = lun << 12;
cmd_pkt->cmd.pkt_a.lun_l4__req_id = lun | req->request_id;
/* upper nibble */
lun = ccb_h->target_lun & 0XF0;
lun = lun << 8;
cmd_pkt->cmd.pkt_a.lun_h4__sgl_entries = lun;
#ifdef TWS_DEBUG
if ( csio->cdb_len > 16 )
TWS_TRACE(sc, "cdb len too big", ccb_h->target_id, csio->cdb_len);
#endif
if(ccb_h->flags & CAM_CDB_POINTER)
bcopy(csio->cdb_io.cdb_ptr, cmd_pkt->cmd.pkt_a.cdb, csio->cdb_len);
else
bcopy(csio->cdb_io.cdb_bytes, cmd_pkt->cmd.pkt_a.cdb, csio->cdb_len);
req->data = ccb;
req->flags |= TWS_DATA_CCB;
/* save ccb ptr */
req->ccb_ptr = ccb;
/*
* tws_map_load_data_callback will fill in the SGL,
* and submit the I/O.
*/
sc->stats.scsi_ios++;
ccb_h->timeout_ch = timeout(tws_timeout, req, (ccb_h->timeout * hz)/1000);
error = tws_map_request(sc, req);
return(error);
}
static int32_t
tws_execute_scsi(struct tws_softc *sc, union ccb *ccb)
{
struct tws_command_packet *cmd_pkt;
struct tws_request *req;
struct ccb_hdr *ccb_h = &(ccb->ccb_h);
struct ccb_scsiio *csio = &(ccb->csio);
int error;
u_int16_t lun;
KKASSERT(lockstatus(&sc->sim_lock, curthread) != 0);
if (ccb_h->target_id >= TWS_MAX_NUM_UNITS) {
TWS_TRACE_DEBUG(sc, "traget id too big", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status |= CAM_TID_INVALID;
xpt_done(ccb);
return(0);
}
if (ccb_h->target_lun >= TWS_MAX_NUM_LUNS) {
TWS_TRACE_DEBUG(sc, "target lun 2 big", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status |= CAM_LUN_INVALID;
xpt_done(ccb);
return(0);
}
if(ccb_h->flags & CAM_CDB_PHYS) {
TWS_TRACE_DEBUG(sc, "cdb phy", ccb_h->target_id, ccb_h->target_lun);
ccb_h->status = CAM_REQ_CMP_ERR;
xpt_done(ccb);
return(0);
}
/*
* We are going to work on this request. Mark it as enqueued (though
* we don't actually queue it...)
*/
ccb_h->status |= CAM_SIM_QUEUED;
req = tws_get_request(sc, TWS_SCSI_IO_REQ);
if ( !req ) {
TWS_TRACE_DEBUG(sc, "no reqs", ccb_h->target_id, ccb_h->target_lun);
/* tws_freeze_simq(sc); */
ccb_h->status |= CAM_REQUEUE_REQ;
xpt_done(ccb);
return(0);
}
if((ccb_h->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
if(ccb_h->flags & CAM_DIR_IN)
req->flags = TWS_DIR_IN;
else
req->flags = TWS_DIR_OUT;
} else {
req->flags = TWS_DIR_NONE; /* no data */
}
req->type = TWS_SCSI_IO_REQ;
req->cb = tws_scsi_complete;
cmd_pkt = req->cmd_pkt;
/* cmd_pkt->hdr.header_desc.size_header = 128; */
cmd_pkt->cmd.pkt_a.res__opcode = TWS_FW_CMD_EXECUTE_SCSI;
cmd_pkt->cmd.pkt_a.unit = ccb_h->target_id;
cmd_pkt->cmd.pkt_a.status = 0;
cmd_pkt->cmd.pkt_a.sgl_offset = 16;
/* lower nibble */
lun = ccb_h->target_lun & 0XF;
lun = lun << 12;
cmd_pkt->cmd.pkt_a.lun_l4__req_id = lun | req->request_id;
/* upper nibble */
lun = ccb_h->target_lun & 0XF0;
lun = lun << 8;
cmd_pkt->cmd.pkt_a.lun_h4__sgl_entries = lun;
#ifdef TWS_DEBUG
if ( csio->cdb_len > 16 )
TWS_TRACE(sc, "cdb len too big", ccb_h->target_id, csio->cdb_len);
#endif
if(ccb_h->flags & CAM_CDB_POINTER)
bcopy(csio->cdb_io.cdb_ptr, cmd_pkt->cmd.pkt_a.cdb, csio->cdb_len);
else
bcopy(csio->cdb_io.cdb_bytes, cmd_pkt->cmd.pkt_a.cdb, csio->cdb_len);
if (!(ccb_h->flags & CAM_DATA_PHYS)) {
/* Virtual data addresses. Need to convert them... */
if (!(ccb_h->flags & CAM_SCATTER_VALID)) {
if (csio->dxfer_len > TWS_MAX_IO_SIZE) {
TWS_TRACE(sc, "I/O is big", csio->dxfer_len, 0);
tws_release_request(req);
ccb_h->status = CAM_REQ_TOO_BIG;
xpt_done(ccb);
return(0);
}
req->length = csio->dxfer_len;
if (req->length) {
req->data = csio->data_ptr;
/* there is 1 sgl_entrie */
/* cmd_pkt->cmd.pkt_a.lun_h4__sgl_entries |= 1; */
}
} else {
TWS_TRACE_DEBUG(sc, "got sglist", ccb_h->target_id, ccb_h->target_lun);
tws_release_request(req);
ccb_h->status = CAM_REQ_CMP_ERR;
xpt_done(ccb);
return(0);
}
} else {
/* Data addresses are physical. */
TWS_TRACE_DEBUG(sc, "Phy data addr", ccb_h->target_id, ccb_h->target_lun);
tws_release_request(req);
ccb_h->status = CAM_REQ_CMP_ERR;
ccb_h->status |= CAM_RELEASE_SIMQ;
ccb_h->status &= ~CAM_SIM_QUEUED;
xpt_done(ccb);
return(0);
}
/* save ccb ptr */
req->ccb_ptr = ccb;
/*
* tws_map_load_data_callback will fill in the SGL,
* and submit the I/O.
*/
sc->stats.scsi_ios++;
callout_reset(ccb_h->timeout_ch, (ccb_h->timeout * hz)/1000,
tws_timeout, req);
error = tws_map_request(sc, req);
return(error);
}