static void push_data(struct device *dev)
{
struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
uint32_t data = 0;
uint32_t f_tx;
DBG_COUNTER_INIT();
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
read_rxflr(info->regs) - 1;
while (f_tx) {
if (spi->tx_buf && spi->tx_buf_len > 0) {
switch (spi->dfs) {
case 1:
data = UNALIGNED_GET((uint8_t *)(spi->tx_buf));
break;
case 2:
data = UNALIGNED_GET((uint16_t *)(spi->tx_buf));
break;
#ifndef CONFIG_ARC
case 4:
data = UNALIGNED_GET((uint32_t *)(spi->tx_buf));
break;
#endif
}
spi->tx_buf += spi->dfs;
spi->tx_buf_len--;
} else if (spi->rx_buf && spi->rx_buf_len > 0) {
/* No need to push more than necessary */
if (spi->rx_buf_len - spi->fifo_diff <= 0) {
break;
}
data = 0;
} else {
/* Nothing to push anymore */
break;
}
write_dr(data, info->regs);
f_tx--;
spi->fifo_diff++;
DBG_COUNTER_INC();
}
if (!spi->tx_buf_len && !spi->rx_buf_len) {
write_txftlr(0, info->regs);
}
DBG("Pushed: %d\n", DBG_COUNTER_RESULT());
}
static void push_data(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
u32_t data = 0;
u32_t f_tx;
DBG_COUNTER_INIT();
if (spi->rx_buf) {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
read_rxflr(info->regs);
if ((int)f_tx < 0) {
f_tx = 0; /* if rx-fifo is full, hold off tx */
}
} else {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs);
}
if (f_tx && (spi->tx_buf_len == 0)) {
/* room in fifo, yet nothing to send */
spi->last_tx = 1; /* setting last_tx indicates TX is done */
}
while (f_tx) {
if (spi->tx_buf && spi->tx_buf_len > 0) {
switch (spi->dfs) {
case 1:
data = UNALIGNED_GET((u8_t *)(spi->tx_buf));
break;
case 2:
data = UNALIGNED_GET((u16_t *)(spi->tx_buf));
break;
#ifndef CONFIG_ARC
case 4:
data = UNALIGNED_GET((u32_t *)(spi->tx_buf));
break;
#endif
}
spi->tx_buf += spi->dfs;
spi->tx_buf_len--;
} else if (spi->rx_buf && spi->rx_buf_len > 0) {
/* No need to push more than necessary */
if (spi->rx_buf_len - spi->fifo_diff <= 0) {
break;
}
data = 0;
} else {
/* Nothing to push anymore */
break;
}
write_dr(data, info->regs);
f_tx--;
spi->fifo_diff++;
DBG_COUNTER_INC();
}
if (spi->last_tx) {
write_txftlr(0, info->regs);
/* prevents any further interrupts demanding TX fifo fill */
}
SYS_LOG_DBG("Pushed: %d", DBG_COUNTER_RESULT());
}
static void push_data(struct device *dev)
{
const struct spi_dw_config *info = dev->config->config_info;
struct spi_dw_data *spi = dev->driver_data;
u32_t data = 0U;
u32_t f_tx;
DBG_COUNTER_INIT();
if (spi_context_rx_on(&spi->ctx)) {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs) -
read_rxflr(info->regs);
if ((int)f_tx < 0) {
f_tx = 0U; /* if rx-fifo is full, hold off tx */
}
} else {
f_tx = DW_SPI_FIFO_DEPTH - read_txflr(info->regs);
}
while (f_tx) {
if (spi_context_tx_buf_on(&spi->ctx)) {
switch (spi->dfs) {
case 1:
data = UNALIGNED_GET((u8_t *)
(spi->ctx.tx_buf));
break;
case 2:
data = UNALIGNED_GET((u16_t *)
(spi->ctx.tx_buf));
break;
#ifndef CONFIG_ARC
case 4:
data = UNALIGNED_GET((u32_t *)
(spi->ctx.tx_buf));
break;
#endif
}
} else if (spi_context_rx_on(&spi->ctx)) {
/* No need to push more than necessary */
if ((int)(spi->ctx.rx_len - spi->fifo_diff) <= 0) {
break;
}
data = 0U;
} else if (spi_context_tx_on(&spi->ctx)) {
data = 0U;
} else {
/* Nothing to push anymore */
break;
}
write_dr(data, info->regs);
spi_context_update_tx(&spi->ctx, spi->dfs, 1);
spi->fifo_diff++;
f_tx--;
DBG_COUNTER_INC();
}
if (!spi_context_tx_on(&spi->ctx)) {
/* prevents any further interrupts demanding TX fifo fill */
write_txftlr(0, info->regs);
}
LOG_DBG("Pushed: %d", DBG_COUNTER_RESULT());
}
char *net_addr_ntop(sa_family_t family, const void *src,
char *dst, size_t size)
{
struct in_addr *addr;
struct in6_addr *addr6;
u16_t *w;
u8_t i, bl, bh, longest = 1;
s8_t pos = -1;
char delim = ':';
unsigned char zeros[8] = { 0 };
char *ptr = dst;
int len = -1;
u16_t value;
bool needcolon = false;
if (family == AF_INET6) {
addr6 = (struct in6_addr *)src;
w = (u16_t *)addr6->s6_addr16;
len = 8;
for (i = 0; i < 8; i++) {
u8_t j;
for (j = i; j < 8; j++) {
if (UNALIGNED_GET(&w[j]) != 0) {
break;
}
zeros[i]++;
}
}
for (i = 0; i < 8; i++) {
if (zeros[i] > longest) {
longest = zeros[i];
pos = i;
}
}
if (longest == 1) {
pos = -1;
}
} else if (family == AF_INET) {
addr = (struct in_addr *)src;
len = 4;
delim = '.';
} else {
return NULL;
}
for (i = 0; i < len; i++) {
/* IPv4 address a.b.c.d */
if (len == 4) {
u8_t l;
value = (u32_t)addr->s4_addr[i];
/* net_byte_to_udec() eats 0 */
if (value == 0) {
*ptr++ = '0';
*ptr++ = delim;
continue;
}
l = net_value_to_udec(ptr, value, 0);
ptr += l;
*ptr++ = delim;
continue;
}
/* IPv6 address */
if (i == pos) {
if (needcolon || i == 0) {
*ptr++ = ':';
}
*ptr++ = ':';
needcolon = false;
i += longest - 1;
continue;
}
if (needcolon) {
*ptr++ = ':';
needcolon = false;
}
value = (u32_t)sys_be16_to_cpu(UNALIGNED_GET(&w[i]));
bh = value >> 8;
bl = value & 0xff;
if (bh) {
if (bh > 0x0f) {
ptr = net_byte_to_hex(ptr, bh, 'a', false);
} else {
if (bh < 10) {
*ptr++ = (char)(bh + '0');
} else {
*ptr++ = (char) (bh - 10 + 'a');
}
}
ptr = net_byte_to_hex(ptr, bl, 'a', true);
} else if (bl > 0x0f) {
ptr = net_byte_to_hex(ptr, bl, 'a', false);
} else {
if (bl < 10) {
*ptr++ = (char)(bl + '0');
} else {
*ptr++ = (char) (bl - 10 + 'a');
}
}
needcolon = true;
}
if (!(ptr - dst)) {
return NULL;
}
if (family == AF_INET) {
*(ptr - 1) = '\0';
} else {
*ptr = '\0';
}
return dst;
}
static int write_op(void *context)
{
struct flash_context *w_ctx = context;
u32_t addr_word;
u32_t tmp_word;
u32_t count;
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)
u32_t ticks_begin = 0;
u32_t ticks_diff;
u32_t i = 1;
if (w_ctx->enable_time_limit) {
ticks_begin = ticker_ticks_now_get();
}
#endif /* CONFIG_SOC_FLASH_NRF_RADIO_SYNC */
/* Start with a word-aligned address and handle the offset */
addr_word = (u32_t)w_ctx->flash_addr & ~0x3;
/* If not aligned, read first word, update and write it back */
if (!is_aligned_32(w_ctx->flash_addr)) {
tmp_word = *(u32_t *)(addr_word);
count = sizeof(u32_t) - (w_ctx->flash_addr & 0x3);
if (count > w_ctx->len) {
count = w_ctx->len;
}
memcpy((u8_t *)&tmp_word + (w_ctx->flash_addr & 0x3),
(void *)w_ctx->data_addr,
count);
nvmc_wait_ready();
*(u32_t *)addr_word = tmp_word;
shift_write_context(count, w_ctx);
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)
if (w_ctx->enable_time_limit) {
ticks_diff =
ticker_ticks_diff_get(ticker_ticks_now_get(),
ticks_begin);
if (2 * ticks_diff >
HAL_TICKER_US_TO_TICKS(w_ctx->slot)) {
nvmc_wait_ready();
return FLASH_OP_ONGOING;
}
}
#endif /* CONFIG_SOC_FLASH_NRF_RADIO_SYNC */
}
/* Write all the 4-byte aligned data */
while (w_ctx->len >= sizeof(u32_t)) {
nvmc_wait_ready();
*(u32_t *)w_ctx->flash_addr =
UNALIGNED_GET((u32_t *)w_ctx->data_addr);
shift_write_context(sizeof(u32_t), w_ctx);
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)
i++;
if (w_ctx->enable_time_limit) {
ticks_diff =
ticker_ticks_diff_get(ticker_ticks_now_get(),
ticks_begin);
if (ticks_diff + ticks_diff/i >
HAL_TICKER_US_TO_TICKS(w_ctx->slot)) {
nvmc_wait_ready();
return FLASH_OP_ONGOING;
}
}
#endif /* CONFIG_SOC_FLASH_NRF_RADIO_SYNC */
}
/* Write remaining data */
if (w_ctx->len) {
tmp_word = *(u32_t *)(w_ctx->flash_addr);
memcpy((u8_t *)&tmp_word, (void *)w_ctx->data_addr, w_ctx->len);
nvmc_wait_ready();
*(u32_t *)w_ctx->flash_addr = tmp_word;
shift_write_context(w_ctx->len, w_ctx);
}
nvmc_wait_ready();
return FLASH_OP_DONE;
}
