u8 NVReadAttr(struct nvidia_par *par, u8 index)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
return (VGA_RD08(par->PCIO, VGA_ATT_R));
}
static int nvidia_gpio_getscl(void *data)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->PCIO, 0x3d5) & 0x04)
val = 1;
val = VGA_RD08(par->PCIO, 0x3d5);
return val;
}
void NVDisablePalette(struct nvidia_par *par)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
par->paletteEnabled = 0;
}
void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
VGA_WR08(par->PCIO, VGA_ATT_W, value);
}
static int riva_gpio_getsda(void* data)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
val = 1;
return val;
}
static void nvidia_gpio_setsda(void *data, int state)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val;
VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
}
static void riva_gpio_setscl(void* data, int state)
{
struct riva_i2c_chan *chan = (struct riva_i2c_chan *)data;
struct riva_par *par = chan->par;
u32 val;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}
u8 NVReadDacMask(struct nvidia_par *par)
{
return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
}
u8 NVReadMiscOut(struct nvidia_par *par)
{
return (VGA_RD08(par->PVIO, VGA_MIS_R));
}
u8 NVReadSeq(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_SEQ_I, index);
return (VGA_RD08(par->PVIO, VGA_SEQ_D));
}
u8 NVReadGr(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_GFX_I, index);
return (VGA_RD08(par->PVIO, VGA_GFX_D));
}
u8 NVReadCrtc(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
}
u8 NVReadDacData(struct nvidia_par *par)
{
return (VGA_RD08(par->PDIO, VGA_PEL_D));
}
static BOOL GenericInit(struct staticdata *sd)
{
D(bug("[NVidia] Generic chip init\n"));
IPTR regs = (IPTR)sd->Card.Registers;
UWORD architecture = sd->Card.Architecture;
UWORD implementation = sd->Card.Chipset;
UWORD implementation_masked = implementation & 0x0FF0;
sd->Card.EnableIRQ = 0;
sd->Card.IO = 0x3d0;
sd->Card.PRAMDAC0 = (ULONG*)(regs + 0x00680000);
sd->Card.PFB = (ULONG*)(regs + 0x00100000);
sd->Card.PFIFO = (ULONG*)(regs + 0x00002000);
sd->Card.PGRAPH = (ULONG*)(regs + 0x00400000);
sd->Card.PEXTDEV = (ULONG*)(regs + 0x00101000);
sd->Card.PTIMER = (ULONG*)(regs + 0x00009000);
sd->Card.PMC = (ULONG*)(regs + 0x00000000);
sd->Card.FIFO = (ULONG*)(regs + 0x00800000);
sd->Card.PCIO0 = (UBYTE*)(regs + 0x00601000);
sd->Card.PDIO0 = (UBYTE*)(regs + 0x00681000);
sd->Card.PVIO = (UBYTE*)(regs + 0x000C0000);
sd->Card.FlatPanel = 0;
sd->Card.twoHeads = (architecture >= NV_ARCH_10) &&
(implementation_masked != 0x0100) &&
(implementation_masked != 0x0150) &&
(implementation_masked != 0x01A0) &&
(implementation_masked != 0x0200);
sd->Card.fpScaler = (sd->Card.twoHeads && (implementation_masked != 0x0110));
sd->Card.twoStagePLL = (implementation_masked == 0x0310) ||
(implementation_masked == 0x0340) ||
(architecture == NV_ARCH_40);
sd->Card.alphaCursor = implementation_masked >= 0x0110;
switch (implementation)
{
case 0x0112:
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017c:
case 0x017d:
case 0x0186:
case 0x0187:
case 0x0286:
case 0x028c:
case 0x0316:
case 0x0317:
case 0x031a:
case 0x031b:
case 0x031c:
case 0x031d:
case 0x031e:
case 0x031f:
case 0x0324:
case 0x0325:
case 0x0326: /* stegerg: checkme, not listed in xfree nv_setup.c */
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
case 0x032e: /* stegerg: checkme, not listed in xfree nv_setup.c */
case 0x0347:
case 0x0349:
case 0x034B:
case 0x034C:
case 0x0160:
case 0x0166:
case 0x00C8:
case 0x00C9:
case 0x00CC:
case 0x0147:
case 0x0148:
case 0x0149:
case 0x014C:
D(bug("[NVidia] Assuming Digital FlatPanel\n"));
sd->Card.FlatPanel = 1;
break;
default:
break;
}
if (architecture == NV_ARCH_04)
nv4GetConfig(sd);
else
nv10GetConfig(sd);
NVSelectHead(sd, 0);
NVLockUnlock(sd, 0);
if (!sd->Card.twoHeads)
{
VGA_WR08(sd->Card.PCIO, 0x3d4, 0x28);
if (VGA_RD08(sd->Card.PCIO, 0x3d5) & 0x80)
sd->Card.FlatPanel = 1;
else
sd->Card.FlatPanel = 0;
}
else
{
UBYTE outputAfromCRTC, outputBfromCRTC;
int CRTCnumber = -1;
UBYTE slaved_on_A, slaved_on_B,tvA=0,tvB=0;
BOOL analog_on_A, analog_on_B;
ULONG oldhead;
UBYTE cr44;
if(implementation_masked != 0x0110) {
if(sd->Card.PRAMDAC0[0x0000052C/4] & 0x100)
outputAfromCRTC = 1;
else
outputAfromCRTC = 0;
if(sd->Card.PRAMDAC0[0x0000252C/4] & 0x100)
outputBfromCRTC = 1;
else
outputBfromCRTC = 0;
analog_on_A = NVIsConnected(sd, 0);
analog_on_B = NVIsConnected(sd, 1);
} else {
outputAfromCRTC = 0;
outputBfromCRTC = 1;
analog_on_A = FALSE;
analog_on_B = FALSE;
}
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
cr44 = VGA_RD08(sd->Card.PCIO, 0x03D5);
VGA_WR08(sd->Card.PCIO, 0x03D5, 3);
NVSelectHead(sd, 1);
NVLockUnlock(sd, 0);
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x28);
slaved_on_B = VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x80;
if(slaved_on_B) {
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x33);
tvB = !(VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x01);
}
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
VGA_WR08(sd->Card.PCIO, 0x03D5, 0);
NVSelectHead(sd, 0);
NVLockUnlock(sd, 0);
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x28);
slaved_on_A = VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x80;
if(slaved_on_A) {
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x33);
tvA = !(VGA_RD08(sd->Card.PCIO, 0x03D5) & 0x01);
}
oldhead = sd->Card.PCRTC0[0x00000860/4];
sd->Card.PCRTC0[0x00000860/4] = oldhead | 0x00000010;
if(slaved_on_A && !tvA) {
CRTCnumber = 0;
sd->Card.FlatPanel = 1;
} else
if(slaved_on_B && !tvB) {
CRTCnumber = 1;
sd->Card.FlatPanel = 1;
} else
if(analog_on_A) {
CRTCnumber = outputAfromCRTC;
sd->Card.FlatPanel = 0;
} else
if(analog_on_B) {
CRTCnumber = outputBfromCRTC;
sd->Card.FlatPanel = 0;
} else
if(slaved_on_A) {
CRTCnumber = 0;
sd->Card.FlatPanel = 1;
sd->Card.Television = 1;
} else
if(slaved_on_B) {
CRTCnumber = 1;
sd->Card.FlatPanel = 1;
sd->Card.Television = 1;
}
if (CRTCnumber == -1)
{
D(bug("[NVidia] Unable to detect CRTC number, using defaults\n"));
if (sd->Card.FlatPanel) sd->Card.CRTCnumber = 1;
else sd->Card.CRTCnumber = 0;
}
else sd->Card.CRTCnumber = CRTCnumber;
if(implementation_masked == 0x0110)
cr44 = sd->Card.CRTCnumber * 0x3;
sd->Card.PCRTC0[0x00000860/4] = oldhead;
VGA_WR08(sd->Card.PCIO, 0x03D4, 0x44);
VGA_WR08(sd->Card.PCIO, 0x03D5, cr44);
NVSelectHead(sd, sd->Card.CRTCnumber);
}
if (sd->Card.FlatPanel && !sd->Card.Television)
{
sd->Card.fpWidth = sd->Card.PRAMDAC[0x0820/4] + 1;
sd->Card.fpHeight= sd->Card.PRAMDAC[0x0800/4] + 1;
}
sd->Card.PRAMDAC[0x0300/4] = 0;
D(bug("[NVidia] Configuration received.\n"));
D(bug("[NVidia] Card has %dMB of video memory\n",
sd->Card.RamAmountKBytes >> 10));
sd->Card.FrameBufferSize = sd->Card.RamAmountKBytes * 1024;
sd->Card.FbUsableSize = sd->Card.FrameBufferSize - 128 * 1024;
D(bug("[NVidia] Max clock is %dMHz\n",
sd->Card.MaxVClockFreqKHz / 1000));
kprintf("\n=== NVidia GenericInit FlatPanel = %d TwoHeads = %d CRTCnumber = %d twostagepll = %d\n\n",
sd->Card.FlatPanel,
sd->Card.twoHeads,
sd->Card.CRTCnumber,
sd->Card.twoStagePLL);
return TRUE;
}
static inline unsigned char MISCin(struct riva_par *par)
{
return (VGA_RD08(par->riva.PVIO, 0x3cc));
}
