static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
switch (port) {
case 0x3d8:
vga.tandy.mode_control=val;
TandyCheckLineMask();
VGA_SetBlinking(val & 0x20);
TANDY_FindMode();
break;
case 0x3d9:
write_color_select(val);
break;
case 0x3da:
vga.tandy.reg_index=val;
break;
// case 0x3db: //Clear lightpen latch
break;
// case 0x3dc: //Preset lightpen latch
break;
// case 0x3dd: //Extended ram page address register:
break;
case 0x3de:
write_tandy_reg(val);
break;
case 0x3df:
vga.tandy.line_mask = val >> 6;
vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
vga.tandy.mem_bank = (val >> 3) & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
TandyCheckLineMask();
VGA_SetupHandlers();
break;
}
}
static void write_tandy_reg(Bit8u val) {
switch (vga.tandy.reg_index) {
case 0x0:
if (machine==MCH_PCJR) {
vga.tandy.mode_control=val;
VGA_SetBlinking(val & 0x20);
PCJr_FindMode();
} else LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
case 0x2: /* Border color */
vga.tandy.border_color=val;
break;
case 0x3: /* More control */
vga.tandy.gfx_control=val;
if (machine==MCH_TANDY) TANDY_FindMode();
else PCJr_FindMode();
break;
/* palette colors */
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b:
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
VGA_ATTR_SetPalette(vga.tandy.reg_index-0x10,val & 0xf);
break;
default:
LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
}
}
static void write_mode_control(Bit8u val) {
/* Check if someone changes the blinking/hi intensity bit */
vga.tandy.mode_control=val;
VGA_SetBlinking((val & 0x20));
if (val & 0x2) {
if (val & 0x10) {
} else VGA_SetMode(M_CGA4);
write_color_select(vga.tandy.color_select); //Setup the correct palette
} else {
VGA_SetMode(M_TEXT);
}
}
static void write_tandy_reg(Bit8u val) {
switch (vga.tandy.reg_index) {
case 0x0:
if (machine==MCH_PCJR) {
vga.tandy.mode_control=val;
VGA_SetBlinking(val & 0x20);
PCJr_FindMode();
} else {
LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
}
break;
case 0x2: /* Border color */
vga.tandy.border_color=val;
break;
case 0x3: /* More control */
vga.tandy.gfx_control=val;
if (machine==MCH_TANDY) TANDY_FindMode();
else PCJr_FindMode();
break;
case 0x5: /* Extended ram page register */
// Bit 0 enables extended ram
// Bit 7 Switches clock, 0 -> cga 28.6 , 1 -> mono 32.5
vga.tandy.extended_ram = val;
//This is a bit of a hack to enable mapping video memory differently for highres mode
TandyCheckLineMask();
VGA_SetupHandlers();
break;
case 0x8: /* Monitor mode seletion */
//Bit 1 select mode e, for 640x200x16, some double clocking thing?
//Bit 4 select 350 line mode for hercules emulation
LOG(LOG_VGAMISC,LOG_NORMAL)("Write %2X to tandy monitor mode",val );
break;
/* palette colors */
case 0x10: case 0x11: case 0x12: case 0x13:
case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b:
case 0x1c: case 0x1d: case 0x1e: case 0x1f:
VGA_ATTR_SetPalette(vga.tandy.reg_index-0x10,val & 0xf);
break;
default:
LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
}
}
static void write_cga(Bitu port,Bitu val,Bitu iolen) {
switch (port) {
case 0x3d8:
vga.tandy.mode_control=val;
if (vga.tandy.mode_control & 0x2) {
if (vga.tandy.mode_control & 0x10) {
if (!(val & 0x4) && machine==MCH_CGA) {
VGA_SetMode(M_CGA16); //Video burst 16 160x200 color mode
} else {
VGA_SetMode(M_TANDY2);
}
} else VGA_SetMode(M_TANDY4);
write_color_select(vga.tandy.color_select);
} else {
VGA_SetMode(M_TANDY_TEXT);
}
VGA_SetBlinking(val & 0x20);
break;
case 0x3d9:
write_color_select(val);
break;
}
}
static void write_tandy(Bitu port,Bitu val,Bitu iolen) {
switch (port) {
case 0x3d8:
vga.tandy.mode_control=val;
VGA_SetBlinking(val & 0x20);
TANDY_FindMode();
break;
case 0x3d9:
write_color_select(val);
break;
case 0x3da:
vga.tandy.reg_index=val;
break;
case 0x3de:
write_tandy_reg(val);
break;
case 0x3df:
vga.tandy.is_32k_mode=(val & 0x80)==0x80;
vga.tandy.disp_bank=val & ((val & 0x80) ? 0x6 : 0x7);
vga.tandy.mem_bank=(val >> 3) & ((val & 0x80) ? 0x6 : 0x7);
VGA_SetupHandlers();
break;
}
}
void write_p3c0(Bitu port,Bitu val,Bitu iolen) {
if (!vga.internal.attrindex) {
attr(index)=val & 0x1F;
vga.internal.attrindex=true;
attr(enabled)=val & 0x20;
/*
0-4 Address of data register to write to port 3C0h or read from port 3C1h
5 If set screen output is enabled and the palette can not be modified,
if clear screen output is disabled and the palette can be modified.
*/
return;
} else {
vga.internal.attrindex=false;
switch (attr(index)) {
/* Palette */
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x04: case 0x05: case 0x06: case 0x07:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0d: case 0x0e: case 0x0f:
if (!attr(enabled)) VGA_ATTR_SetPalette(attr(index),val);
/*
0-5 Index into the 256 color DAC table. May be modified by 3C0h index
10h and 14h.
*/
break;
case 0x10: /* Mode Control Register */
if (!IS_VGA_ARCH) val&=0x1f; // not really correct, but should do it
if ((attr(mode_control) ^ val) & 0x80) {
attr(mode_control)^=0x80;
for (Bitu i=0;i<0x10;i++) {
VGA_ATTR_SetPalette(i,vga.attr.palette[i]);
}
}
if ((attr(mode_control) ^ val) & 0x08) {
VGA_SetBlinking(val & 0x8);
}
if ((attr(mode_control) ^ val) & 0x04) {
attr(mode_control)=val;
VGA_DetermineMode();
if ((IS_VGA_ARCH) && (svgaCard==SVGA_None)) VGA_StartResize();
} else {
attr(mode_control)=val;
VGA_DetermineMode();
}
/*
0 Graphics mode if set, Alphanumeric mode else.
1 Monochrome mode if set, color mode else.
2 9-bit wide characters if set.
The 9th bit of characters C0h-DFh will be the same as
the 8th bit. Otherwise it will be the background color.
3 If set Attribute bit 7 is blinking, else high intensity.
5 If set the PEL panning register (3C0h index 13h) is temporarily set
to 0 from when the line compare causes a wrap around until the next
vertical retrace when the register is automatically reloaded with
the old value, else the PEL panning register ignores line compares.
6 If set pixels are 8 bits wide. Used in 256 color modes.
7 If set bit 4-5 of the index into the DAC table are taken from port
3C0h index 14h bit 0-1, else the bits in the palette register are
used.
*/
break;
case 0x11: /* Overscan Color Register */
attr(overscan_color)=val;
/* 0-5 Color of screen border. Color is defined as in the palette registers. */
break;
case 0x12: /* Color Plane Enable Register */
/* Why disable colour planes? */
attr(color_plane_enable)=val;
/*
0 Bit plane 0 is enabled if set.
1 Bit plane 1 is enabled if set.
2 Bit plane 2 is enabled if set.
3 Bit plane 3 is enabled if set.
4-5 Video Status MUX. Diagnostics use only.
Two attribute bits appear on bits 4 and 5 of the Input Status
Register 1 (3dAh). 0: Bit 2/0, 1: Bit 5/4, 2: bit 3/1, 3: bit 7/6
*/
break;
case 0x13: /* Horizontal PEL Panning Register */
attr(horizontal_pel_panning)=val & 0xF;
switch (vga.mode) {
case M_TEXT:
if ((val==0x7) && (svgaCard==SVGA_None)) vga.config.pel_panning=7;
if (val>0x7) vga.config.pel_panning=0;
else vga.config.pel_panning=val+1;
break;
case M_VGA:
case M_LIN8:
vga.config.pel_panning=(val & 0x7)/2;
break;
case M_LIN16:
default:
vga.config.pel_panning=(val & 0x7);
}
/*
0-3 Indicates number of pixels to shift the display left
Value 9bit textmode 256color mode Other modes
0 1 0 0
1 2 n/a 1
2 3 1 2
3 4 n/a 3
4 5 2 4
5 6 n/a 5
6 7 3 6
7 8 n/a 7
8 0 n/a n/a
*/
break;
case 0x14: /* Color Select Register */
if (!IS_VGA_ARCH) {
attr(color_select)=0;
break;
}
if (attr(color_select) ^ val) {
attr(color_select)=val;
for (Bitu i=0;i<0x10;i++) {
VGA_ATTR_SetPalette(i,vga.attr.palette[i]);
}
}
/*
0-1 If 3C0h index 10h bit 7 is set these 2 bits are used as bits 4-5 of
the index into the DAC table.
2-3 These 2 bits are used as bit 6-7 of the index into the DAC table
except in 256 color mode.
Note: this register does not affect 256 color modes.
*/
break;
default:
if (svga.write_p3c0) {
svga.write_p3c0(attr(index), val, iolen);
break;
}
LOG(LOG_VGAMISC,LOG_NORMAL)("VGA:ATTR:Write to unkown Index %2X",attr(index));
break;
}
}
}
