void vidc_720p_encode_set_seq_header_buffer(u32 n_ext_buffer_start,
					     u32 n_ext_buffer_end,
					     u32 n_start_byte_num)
{
	VIDC_IO_OUT(REG_275113_ADDR, n_ext_buffer_start);

	VIDC_IO_OUT(REG_87912, n_ext_buffer_start);

	VIDC_IO_OUT(REG_988007_ADDR, n_ext_buffer_end);

	VIDC_IO_OUT(REG_66693, n_start_byte_num);
}
Exemplo n.º 2
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void vidc_720p_encode_set_vop_time(u32 vop_time_resolution,
				    u32 vop_time_increment)
{
	u32 enable_vop, vop_timing_reg;
	if (!vop_time_resolution)
		VIDC_IO_OUT(REG_64895, 0x0);
	else {
		enable_vop = 0x1;
		vop_timing_reg = (enable_vop << 0x1f) |
		(vop_time_resolution << 0x10) | vop_time_increment;
		VIDC_IO_OUT(REG_64895, vop_timing_reg);
	}
}
Exemplo n.º 3
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u32 vidc_720p_engine_reset(u32 ch_id,
	enum vidc_720p_endian dma_endian,
	enum vidc_720p_interrupt_level_selection interrupt_sel,
	u32 interrupt_mask
)
{
	u32 op_done = 0;
	u32 counter = 0;

	VIDC_LOGERR_STRING("ENG-RESET!!");
	/* issue the engine reset command */
	vidc_720p_submit_command(ch_id, VIDC_720P_CMD_MFC_ENGINE_RESET);

	do {
		VIDC_BUSY_WAIT(20);
		VIDC_IO_IN(REG_982553, &op_done);
		counter++;
	} while (!op_done && counter < 10);

	if (!op_done) {
		/* Reset fails */
		return  false ;
	}

	/* write invalid channel id */
	VIDC_IO_OUT(REG_97293, 4);

	/* Set INT_PULSE_SEL */
	if (interrupt_sel == VIDC_720P_INTERRUPT_LEVEL_SEL)
		VIDC_IO_OUT(REG_491082, 0);
	else
		VIDC_IO_OUT(REG_491082, 1);

	if (!interrupt_mask) {
		/* Disable interrupt */
		VIDC_IO_OUT(REG_609676, 1);
	} else {
	  /* Enable interrupt */
		VIDC_IO_OUT(REG_609676, 0);
	}

	/* Clear any pending interrupt */
	VIDC_IO_OUT(REG_614776, 1);

	/* Set INT_ENABLE_REG */
	VIDC_IO_OUT(REG_418173, interrupt_mask);

	/*Sets the DMA endianness */
	VIDC_IO_OUT(REG_736316, dma_endian);

	/*Restore ARM endianness */
	VIDC_IO_OUT(REG_215724, 0);

	/* retun engine reset success */
	return true ;
}
Exemplo n.º 4
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void vidc_720p_encode_set_multi_slice_info(enum
					    vidc_720p_MSlice_selection
					    m_slice_sel,
					    u32 multi_slice_size)
{
	switch (m_slice_sel) {
	case VIDC_720P_MSLICE_BY_MB_COUNT:
		{
			VIDC_IO_OUT(REG_588301, 0x1);
			VIDC_IO_OUT(REG_1517, m_slice_sel);
			VIDC_IO_OUT(REG_105335, multi_slice_size);
			break;
		}
	case VIDC_720P_MSLICE_BY_BYTE_COUNT:
		{
			VIDC_IO_OUT(REG_588301, 0x1);
			VIDC_IO_OUT(REG_1517, m_slice_sel);
			VIDC_IO_OUT(REG_561679, multi_slice_size);
			break;
		}
	case VIDC_720P_MSLICE_BY_GOB:
		{
			VIDC_IO_OUT(REG_588301, 0x1);
			break;
		}
	default:
	case VIDC_720P_MSLICE_OFF:
		{
			VIDC_IO_OUT(REG_588301, 0x0);
			break;
		}
	}
}
Exemplo n.º 5
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void vidc_720p_decode_bitstream_header(u32 ch_id,
					u32 dec_unit_size,
					u32 start_byte_num,
					u32 ext_buffer_start,
					u32 ext_buffer_end,
					enum
					vidc_720p_memory_access_method
					memory_access_model,
					u32 decode_order)
{
	VIDC_IO_OUT(REG_965480, decode_order);

	VIDC_IO_OUT(REG_639999, 0x8080);

	VIDC_IO_OUT(REG_275113_ADDR, ext_buffer_start);

	VIDC_IO_OUT(REG_988007_ADDR, ext_buffer_end);

	VIDC_IO_OUT(REG_87912, ext_buffer_end);

	VIDC_IO_OUT(REG_761892, dec_unit_size);

	VIDC_IO_OUT(REG_66693, start_byte_num);

	VIDC_IO_OUT(REG_841539, memory_access_model);

	vidc_720p_submit_command(ch_id, VIDC_720P_CMD_INITCODEC);
}
Exemplo n.º 6
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void vidc_720p_encode_set_rc_config(u32 enable_frame_level_rc,
				     u32 enable_mb_level_rc_flag,
				     u32 i_frame_qp, u32 pframe_qp)
{
   u32 rc_config = i_frame_qp;

	if (enable_frame_level_rc)
		rc_config |= (0x1 << 0x9);

	if (enable_mb_level_rc_flag)
		rc_config |= (0x1 << 0x8);

	VIDC_IO_OUT(REG_58211, rc_config);
	VIDC_IO_OUT(REG_548359, pframe_qp);
}
Exemplo n.º 7
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void vidc_720p_encode_init_codec(u32 i_ch_id,
				  enum vidc_720p_memory_access_method
				  memory_access_model)
{

	VIDC_IO_OUT(REG_841539, memory_access_model);
	vidc_720p_submit_command(i_ch_id, VIDC_720P_CMD_INITCODEC);
}
void vidc_720p_decode_bitstream_header(u32 n_ch_id,
					u32 n_dec_unit_size,
					u32 n_start_byte_num,
					u32 n_ext_buffer_start,
					u32 n_ext_buffer_end,
					enum
					vidc_720p_memory_access_method_type
					e_memory_access_model)
{
	VIDC_IO_OUT(REG_965480, 0x0);

	VIDC_IO_OUT(REG_275113_ADDR, n_ext_buffer_start);

	VIDC_IO_OUT(REG_988007_ADDR, n_ext_buffer_end);

	VIDC_IO_OUT(REG_87912, n_ext_buffer_end);

	VIDC_IO_OUT(REG_761892, n_dec_unit_size);

	VIDC_IO_OUT(REG_66693, n_start_byte_num);

	VIDC_IO_OUT(REG_841539, e_memory_access_model);

	vidc_720p_submit_command(n_ch_id, VIDC_720P_CMD_INITCODEC);
}
Exemplo n.º 9
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u32 vidc_720p_do_sw_reset(void)
{

	u32 fw_start = 0;
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_224135, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_193553, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_141269, 1);
	VIDC_BUSY_WAIT(15);
	VIDC_IO_OUT(REG_141269, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_IN(REG_193553, &fw_start);

	if (!fw_start) {
		DBG("\n VIDC-SW-RESET-FAILS!");
		return false;
	}
	return true;
}
u32 vidc_720p_do_sw_reset(void)
{

	u32 n_fw_start = 0;
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_224135, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_193553, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_OUT(REG_141269, 1);
	VIDC_BUSY_WAIT(15);
	VIDC_IO_OUT(REG_141269, 0);
	VIDC_BUSY_WAIT(5);
	VIDC_IO_IN(REG_193553, &n_fw_start);

	if (!n_fw_start) {
		DBG("\n VIDC-SW-RESET-FAILS!");
		return FALSE;
	}
	return TRUE;
}
Exemplo n.º 11
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void vidc_720p_encode_set_db_filter_control(enum vidc_720p_DBConfig
					     db_config,
					     u32 i_slice_alpha_offset,
					     u32 i_slice_beta_offset)
{
	u32 deblock_params;
	deblock_params = (u32)db_config;
	deblock_params |=
		((i_slice_beta_offset << 0x2) | (i_slice_alpha_offset << 0x7));

	/* Write deblocking control settings */
	VIDC_IO_OUT(REG_458130, deblock_params);
}
Exemplo n.º 12
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u32 vidc_720p_reset_is_success()
{
	u32 stagecounter = 0;
	VIDC_IO_IN(REG_352831, &stagecounter);
	stagecounter &= 0xff;
	if (stagecounter != 0xe5) {
		DBG("\n VIDC-CPU_RESET-FAILS!");
		VIDC_IO_OUT(REG_224135, 0);
		msleep(10);
		return false;
	}
	return true;
}
u32 vidc_720p_reset_is_success()
{
	u32 n_stagecounter = 0;
	VIDC_IO_IN(REG_352831, &n_stagecounter);
	n_stagecounter &= 0xff;
	if (n_stagecounter != 0xe5) {
		DBG("\n VIDC-CPU_RESET-FAILS!");
		VIDC_IO_OUT(REG_224135, 0);
		msleep(10);
		return FALSE;
	}
	return TRUE;
}
Exemplo n.º 14
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void vidc_720p_encode_set_entropy_control(enum vidc_720p_entropy_sel
					   entropy_sel,
					   enum vidc_720p_cabac_model
					   cabac_model_number)
{
	u32 num;
	u32 entropy_params = (u32)entropy_sel;
	/* Set Model Number */
	if (entropy_sel == VIDC_720P_ENTROPY_SEL_CABAC) {
		num = (u32)cabac_model_number;
		entropy_params |= (num << 0x2);
	}
	/* Set Entropy parameters */
	VIDC_IO_OUT(REG_504878, entropy_params);
}
Exemplo n.º 15
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void vidc_720p_encode_set_mb_level_rc_params(u32 dark_region_as_flag,
					      u32 smooth_region_as_flag,
					      u32 static_region_as_flag,
					      u32 activity_region_flag)
{
	u32 mb_level_rc = 0x0;
	if (activity_region_flag)
		mb_level_rc |= 0x1;
	if (static_region_as_flag)
		mb_level_rc |= (0x1 << 0x1);
	if (smooth_region_as_flag)
		mb_level_rc |= (0x1 << 0x2);
	if (dark_region_as_flag)
		mb_level_rc |= (0x1 << 0x3);
	/* Write MB level rate control */
	VIDC_IO_OUT(REG_995041, mb_level_rc);
}
Exemplo n.º 16
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void vidc_720p_start_cpu(enum vidc_720p_endian dma_endian,
						  u32 *icontext_bufferstart,
						  u32 *debug_core_dump_addr,
						  u32  debug_buffer_size)
{
	u32 dbg_info_input0_reg = 0x1;
	VIDC_IO_OUT(REG_361582, 0);
	VIDC_IO_OUT(REG_958768, icontext_bufferstart);
	VIDC_IO_OUT(REG_736316, dma_endian);
	if (debug_buffer_size) {
		dbg_info_input0_reg = (debug_buffer_size << 0x10)
			| (0x2 << 1) | 0x1;
		VIDC_IO_OUT(REG_166247, debug_core_dump_addr);
	}
	VIDC_IO_OUT(REG_699747, dbg_info_input0_reg);
	VIDC_IO_OUT(REG_224135, 1);
}
Exemplo n.º 17
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void vidc_720p_decode_frame(u32 ch_id, u32 ext_buffer_start,
			     u32 ext_buffer_end, u32 dec_unit_size,
			     u32 start_byte_num, u32 input_frame_tag)
{
	VIDC_IO_OUT(REG_275113_ADDR, ext_buffer_start);

	VIDC_IO_OUT(REG_988007_ADDR, ext_buffer_end);

	VIDC_IO_OUT(REG_87912, ext_buffer_end);

	VIDC_IO_OUT(REG_66693, start_byte_num);

	VIDC_IO_OUT(REG_94750, input_frame_tag);

	VIDC_IO_OUT(REG_761892, dec_unit_size);

	vidc_720p_submit_command(ch_id, VIDC_720P_CMD_FRAMERUN);
}
Exemplo n.º 18
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void vidc_720p_encode_frame(u32 ch_id,
			     u32 ext_buffer_start,
			     u32 ext_buffer_end,
			     u32 start_byte_number, u32 y_addr,
			     u32 c_addr)
{
	VIDC_IO_OUT(REG_275113_ADDR, ext_buffer_start);

	VIDC_IO_OUT(REG_988007_ADDR, ext_buffer_end);

	VIDC_IO_OUT(REG_87912, ext_buffer_start);

	VIDC_IO_OUT(REG_66693, start_byte_number);

	VIDC_IO_OUT(REG_99105, y_addr);

	VIDC_IO_OUT(REG_777113_ADDR, c_addr);

	vidc_720p_submit_command(ch_id, VIDC_720P_CMD_FRAMERUN);
}
Exemplo n.º 19
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void vidc_720p_decode_dynamic_req_reset(void)
{
	VIDC_IO_OUT(REG_76706, 0x0);
	VIDC_IO_OUT(REG_147682, 0x0);
	VIDC_IO_OUT(REG_896825, 0x0);
}
Exemplo n.º 20
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void vidc_720p_metadata_enable(u32 flag, u32 *input_buffer)
{
	VIDC_IO_OUT(REG_854681, flag);
	VIDC_IO_OUT(REG_988552, input_buffer);
}
Exemplo n.º 21
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void vidc_720p_decode_setH264VSPBuffer(u32 *pi_vsp_temp_buffer_start)
{
	VIDC_IO_OUT(REG_958768, pi_vsp_temp_buffer_start);
}
Exemplo n.º 22
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void vidc_720p_decode_set_mpeg4_data_partitionbuffer(u32 *vsp_buf_start)
{
    VIDC_IO_OUT(REG_958768, vsp_buf_start);
}
Exemplo n.º 23
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void vidc_720p_encode_set_control_param(u32 param_val)
{
	VIDC_IO_OUT(REG_128234, param_val);
}
Exemplo n.º 24
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void vidc_720p_encode_unalign_bitstream(u32 upper_unalign_word,
					 u32 lower_unalign_word)
{
	VIDC_IO_OUT(REG_792026, upper_unalign_word);
	VIDC_IO_OUT(REG_844152, lower_unalign_word);
}
Exemplo n.º 25
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void vidc_720p_encode_set_frame_level_rc_params(u32 i_reaction_coeff)
{
	VIDC_IO_OUT(REG_677784, i_reaction_coeff);
}
Exemplo n.º 26
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void vidc_720p_encode_set_i_period(u32 i_i_period)
{
	VIDC_IO_OUT(REG_950374, i_i_period);
}
Exemplo n.º 27
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void vidc_720p_decode_setpassthrough_start(u32 pass_startaddr)
{
	VIDC_IO_OUT(REG_486169, pass_startaddr);
}
Exemplo n.º 28
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void vidc_720p_decode_set_dpb_release_buffer_mask(u32
						   i_dpb_release_buffer_mask)
{
	VIDC_IO_OUT(REG_603032, i_dpb_release_buffer_mask);
}
Exemplo n.º 29
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void vidc_720p_encode_set_dpb_buffer(u32 *pi_enc_dpb_addr, u32 alloc_len)
{
	VIDC_IO_OUT(REG_341928_ADDR, pi_enc_dpb_addr);
	VIDC_IO_OUT(REG_319934, alloc_len);
}
Exemplo n.º 30
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void vidc_720p_encode_set_intra_refresh_mb_number(u32 i_cir_mb_number)
{
	VIDC_IO_OUT(REG_857491, i_cir_mb_number);
}