/* SPI2 pinmux */ DEFAULT_PINMUX(ULPI_DATA4, SPI2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA5, SPI2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA6, SPI2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7, SPI2, PULL_UP, NORMAL, INPUT), /* I2S 2 */ DEFAULT_PINMUX(DAP3_FS, I2S2, PULL_DOWN, NORMAL, INPUT), DEFAULT_PINMUX(DAP3_DIN, I2S2, PULL_DOWN, NORMAL, INPUT), DEFAULT_PINMUX(DAP3_DOUT, I2S2, PULL_DOWN, NORMAL, OUTPUT), DEFAULT_PINMUX(DAP3_SCLK, I2S2, PULL_DOWN, NORMAL, INPUT), VI_PINMUX(VI_D0, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D1, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D2, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D3, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D4, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D5, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D6, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D7, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D8, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D9, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D10, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D11, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_PCLK, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_HSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_VSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_MCLK, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE),
return -ENODEV;
}
static int pluto_focuser_power_off(struct ad5816_power_rail *pw)
{
if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c)))
return -EFAULT;
regulator_disable(pw->vdd);
regulator_disable(pw->vdd_i2c);
return 0;
}
static struct tegra_pingroup_config mclk_disable =
VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
static struct tegra_pingroup_config mclk_enable =
VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
static struct tegra_pingroup_config pbb0_disable =
VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
static struct tegra_pingroup_config pbb0_enable =
VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT);
/*
* more regulators need to be allocated to activate the sensor devices.
* pluto_vcmvdd: this is a workaround due to the focuser device(AD5816) will
* hook up the i2c bus if it is not powered up.
* pluto_i2cvdd: by default, the power supply on the i2c bus is OFF. So it
DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_WR_N, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), /* pin config for gpios */ DEFAULT_PINMUX(VI_D0, SAFE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_OUT, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_REQ, RSVD2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, TRISTATE, INPUT),
// DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT),
CEC_PINMUX(HDMI_CEC, CEC, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE),
DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT),
/* Gpios */
/* SDMMC1 CD gpio */
DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT),//
/* SDMMC1 WP gpio */
DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT),
/* Power rails GPIO */
VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
VI_PINMUX(VI_PCLK, RSVD1, PULL_UP, TRISTATE, INPUT, DISABLE, ENABLE),
VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
};
int __init x3_pinmux_init(void)
{
tegra_pinmux_config_table(x3_pinmux, ARRAY_SIZE(x3_pinmux));
tegra_drive_pinmux_config_table(x3_drive_pinmux,
ARRAY_SIZE(x3_drive_pinmux));
return 0;
//VI DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D11, RSVD1, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D3, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D4, VI, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D5, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D6, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D7, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D8, SDMMC2, NORMAL, TRISTATE, OUTPUT), DEFAULT_PINMUX(VI_D9, SDMMC2, NORMAL, TRISTATE, OUTPUT), VI_PINMUX(VI_HSYNC, RSVD1, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), DEFAULT_PINMUX(VI_MCLK, VI, NORMAL, TRISTATE, INPUT), VI_PINMUX(VI_PCLK, RSVD1, NORMAL, TRISTATE, INPUT, DISABLE, ENABLE), VI_PINMUX(VI_VSYNC, RSVD1, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), //DDR //DSI_CSI //HDMI //HSIC //IC_USB //PCIe
DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, OUTPUT), /* PCIE */ DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_RST_N, PCIE, PULL_UP, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, PULL_UP, NORMAL, OUTPUT), VI_PINMUX(VI_D2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D8, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D9, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_PCLK, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_HSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_VSYNC, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), /* pin config for gpios */ DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(LCD_CS1_N, RSVD2, PULL_UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, OUTPUT), /* CAM2_LDO3_EN */
DEFAULT_PINMUX(GMI_A19, SPI4, PULL_UP, NORMAL, OUTPUT), /* EN_VDD_BL1 */
DEFAULT_PINMUX(LCD_M1, DISPLAYA, PULL_UP, NORMAL, OUTPUT), /* EN_VDD_PNL1 */
DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), /* EN_3V3_FUSE */
DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, OUTPUT), /* EN_GPS_1V8 */
DEFAULT_PINMUX(CLK2_REQ, DAP, NORMAL, NORMAL, OUTPUT), /* EN_WLAN_1V8 */
DEFAULT_PINMUX(GPIO_PV2, OWR, NORMAL, NORMAL, OUTPUT), /* EN_GPS_3V3 */
DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), /* EN_WLAN_3V3 */
DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_UP, NORMAL, OUTPUT), /* LS_3V3_EN */
DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, NORMAL, OUTPUT), /* CAM1_LDO1_EN */
DEFAULT_PINMUX(KB_ROW7, KBC, NORMAL, NORMAL, OUTPUT), /* CAM2_LDO1_EN */
/* These pinmuxs should be not available in T30S */
VI_PINMUX(VI_D6, VI, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_D8, SDMMC2, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_D9, SDMMC2, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_D11, RSVD1, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_PCLK, RSVD1, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_HSYNC, RSVD1, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
VI_PINMUX(VI_VSYNC, RSVD1, PULL_DOWN, TRISTATE, OUTPUT, DISABLE, DISABLE),
};
/* pinmux: please add avalon-specific pinmux here */
static __initdata struct tegra_pingroup_config avalon_pinmux[] = {
/* pingrp mux pupd tri io */
DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), /* WW_WAKE */
DEFAULT_PINMUX(SPDIF_IN, SPDIF, PULL_UP, TRISTATE, OUTPUT), /* unused */
DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, OUTPUT), /* R_NFC_VEN_EE */
DEFAULT_PINMUX(SPI1_MOSI, SPI1, PULL_UP, TRISTATE, OUTPUT), /* unused */
