/**
* Process raw-mode specific forced actions.
*
* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
*
* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
* EM statuses.
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
* @param pCtx Pointer to the guest CPU context.
*/
static int emR3HmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
{
/*
* Sync page directory.
*/
if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
{
Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
#ifdef VBOX_WITH_RAW_MODE
Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
#endif
/* Prefetch pages for EIP and ESP. */
/** @todo This is rather expensive. Should investigate if it really helps at all. */
rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
if (rc == VINF_SUCCESS)
rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
if (rc != VINF_SUCCESS)
{
if (rc != VINF_PGM_SYNC_CR3)
{
AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
return rc;
}
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
}
/** @todo maybe prefetch the supervisor stack page as well */
#ifdef VBOX_WITH_RAW_MODE
Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
#endif
}
/*
* Allocate handy pages (just in case the above actions have consumed some pages).
*/
if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
{
int rc = PGMR3PhysAllocateHandyPages(pVM);
if (RT_FAILURE(rc))
return rc;
}
/*
* Check whether we're out of memory now.
*
* This may stem from some of the above actions or operations that has been executed
* since we ran FFs. The allocate handy pages must for instance always be followed by
* this check.
*/
if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
return VINF_EM_NO_MEMORY;
return VINF_SUCCESS;
}
/**
* Default VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVMCPU Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3DefaultWait(PUVMCPU pUVCpu)
{
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1000);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
selmGuestGDTWriteHandler(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtr, void *pvPtr, void *pvBuf, size_t cbBuf,
PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
{
Assert(enmAccessType == PGMACCESSTYPE_WRITE);
NOREF(enmAccessType);
Log(("selmGuestGDTWriteHandler: write to %RGv size %d\n", GCPtr, cbBuf));
NOREF(GCPtr);
NOREF(cbBuf);
NOREF(pvPtr);
NOREF(pvBuf);
NOREF(enmOrigin);
NOREF(pvUser);
# ifdef IN_RING3
VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
return VINF_PGM_HANDLER_DO_DEFAULT;
# else /* IN_RC: */
/*
* Execute the write, doing necessary pre and post shadow GDT checks.
*/
PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
uint32_t offGuestGdt = pCtx->gdtr.pGdt - GCPtr;
selmRCGuestGdtPreWriteCheck(pVM, pVCpu, offGuestGdt, cbBuf, pCtx);
memcpy(pvBuf, pvPtr, cbBuf);
VBOXSTRICTRC rcStrict = selmRCGuestGdtPostWriteCheck(pVM, pVCpu, offGuestGdt, cbBuf, pCtx);
if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTHandled);
else
STAM_COUNTER_INC(&pVM->selm.s.StatRCWriteGuestGDTUnhandled);
return rcStrict;
# endif
}
/**
* The global 1 halt method - VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVCpu Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3HaltGlobal1Wait(PUVMCPU pUVCpu)
{
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
PVM pVM = pUVCpu->pUVM->pVM;
PVMCPU pVCpu = VMMGetCpu(pVM);
Assert(pVCpu->idCpu == pUVCpu->idCpu);
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_HALT, RTTimeNanoTS() + 1000000000 /* +1s */, NULL);
if (rc == VERR_INTERRUPTED)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "vmR3HaltGlobal1Wait: VMMR0_DO_GVMM_SCHED_HALT->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Suspended VM Wait.
* Only a handful of forced actions will cause the function to
* return to the caller.
*
* @returns VINF_SUCCESS unless a fatal error occurred. In the latter
* case an appropriate status code is returned.
* @param pUVCpu Pointer to the user mode VMCPU structure.
* @thread The emulation thread.
* @internal
*/
VMMR3_INT_DECL(int) VMR3WaitU(PUVMCPU pUVCpu)
{
LogFlow(("VMR3WaitU:\n"));
/*
* Check Relevant FFs.
*/
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
if ( pVM
&& ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK)
)
)
{
LogFlow(("VMR3Wait: returns VINF_SUCCESS (FF %#x)\n", pVM->fGlobalForcedActions));
return VINF_SUCCESS;
}
/*
* Do waiting according to the halt method (so VMR3NotifyFF
* doesn't have to special case anything).
*/
PUVM pUVM = pUVCpu->pUVM;
int rc = g_aHaltMethods[pUVM->vm.s.iHaltMethod].pfnWait(pUVCpu);
LogFlow(("VMR3WaitU: returns %Rrc (FF %#x)\n", rc, pUVM->pVM ? pUVM->pVM->fGlobalForcedActions : 0));
return rc;
}
/**
* Bootstrap VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVMCPU Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3BootstrapWait(PUVMCPU pUVCpu)
{
PUVM pUVM = pUVCpu->pUVM;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if (pUVM->vm.s.pNormalReqs || pUVM->vm.s.pPriorityReqs) /* global requests pending? */
break;
if (pUVCpu->vm.s.pNormalReqs || pUVCpu->vm.s.pPriorityReqs) /* local requests pending? */
break;
if ( pUVCpu->pVM
&& ( VM_FF_IS_PENDING(pUVCpu->pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_IS_PENDING(VMMGetCpu(pUVCpu->pVM), VMCPU_FF_EXTERNAL_SUSPENDED_MASK)
)
)
break;
if (pUVM->vm.s.fTerminateEMT)
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1000);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Executes instruction in HM mode if we can.
*
* This is somewhat comparable to REMR3EmulateInstruction.
*
* @returns VBox strict status code.
* @retval VINF_EM_DBG_STEPPED on success.
* @retval VERR_EM_CANNOT_EXEC_GUEST if we cannot execute guest instructions in
* HM right now.
*
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure for the calling EMT.
* @param fFlags Combinations of EM_ONE_INS_FLAGS_XXX.
* @thread EMT.
*/
VMMR3_INT_DECL(VBOXSTRICTRC) EMR3HmSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
{
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
Assert(!(fFlags & ~EM_ONE_INS_FLAGS_MASK));
if (!HMR3CanExecuteGuest(pVM, pCtx))
return VINF_EM_RESCHEDULE;
uint64_t const uOldRip = pCtx->rip;
for (;;)
{
/*
* Service necessary FFs before going into HM.
*/
if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
{
VBOXSTRICTRC rcStrict = emR3HmForcedActions(pVM, pVCpu, pCtx);
if (rcStrict != VINF_SUCCESS)
{
Log(("EMR3HmSingleInstruction: FFs before -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
return rcStrict;
}
}
/*
* Go execute it.
*/
bool fOld = HMSetSingleInstruction(pVM, pVCpu, true);
VBOXSTRICTRC rcStrict = VMMR3HmRunGC(pVM, pVCpu);
HMSetSingleInstruction(pVM, pVCpu, fOld);
LogFlow(("EMR3HmSingleInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
/*
* Handle high priority FFs and informational status codes. We don't do
* normal FF processing the caller or the next call can deal with them.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
{
rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
LogFlow(("EMR3HmSingleInstruction: FFs after -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
}
if (rcStrict != VINF_SUCCESS && (rcStrict < VINF_EM_FIRST || rcStrict > VINF_EM_LAST))
{
rcStrict = emR3HmHandleRC(pVM, pVCpu, pCtx, VBOXSTRICTRC_TODO(rcStrict));
Log(("EMR3HmSingleInstruction: emR3HmHandleRC -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
}
/*
* Done?
*/
if ( (rcStrict != VINF_SUCCESS && rcStrict != VINF_EM_DBG_STEPPED)
|| !(fFlags & EM_ONE_INS_FLAGS_RIP_CHANGE)
|| pCtx->rip != uOldRip)
{
if (rcStrict == VINF_SUCCESS && pCtx->rip != uOldRip)
rcStrict = VINF_EM_DBG_STEPPED;
Log(("EMR3HmSingleInstruction: returns %Rrc (rip %llx -> %llx)\n", VBOXSTRICTRC_VAL(rcStrict), uOldRip, pCtx->rip));
return rcStrict;
}
}
}
/**
* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
*
* This function contains the raw-mode version of the inner
* execution loop (the outer loop being in EMR3ExecuteVM()).
*
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM The cross context VM structure.
* @param pVCpu The cross context virtual CPU structure.
* @param pfFFDone Where to store an indicator telling whether or not
* FFs were done before returning.
*/
int emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
{
int rc = VERR_IPE_UNINITIALIZED_STATUS;
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
LogFlow(("emR3HmExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
*pfFFDone = false;
STAM_COUNTER_INC(&pVCpu->em.s.StatHmExecuteEntry);
#ifdef EM_NOTIFY_HM
HMR3NotifyScheduled(pVCpu);
#endif
/*
* Spin till we get a forced action which returns anything but VINF_SUCCESS.
*/
for (;;)
{
STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHmEntry, a);
/* Check if a forced reschedule is pending. */
if (HMR3IsRescheduleRequired(pVM, pCtx))
{
rc = VINF_EM_RESCHEDULE;
break;
}
/*
* Process high priority pre-execution raw-mode FFs.
*/
#ifdef VBOX_WITH_RAW_MODE
Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
#endif
if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
{
rc = emR3HmForcedActions(pVM, pVCpu, pCtx);
if (rc != VINF_SUCCESS)
break;
}
#ifdef LOG_ENABLED
/*
* Log important stuff before entering GC.
*/
if (TRPMHasTrap(pVCpu))
Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
uint32_t cpl = CPUMGetGuestCPL(pVCpu);
if (pVM->cCpus == 1)
{
if (pCtx->eflags.Bits.u1VM)
Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
else
{
if (pCtx->eflags.Bits.u1VM)
Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
#endif /* LOG_ENABLED */
/*
* Execute the code.
*/
STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHmEntry, a);
if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
{
STAM_PROFILE_START(&pVCpu->em.s.StatHmExec, x);
rc = VMMR3HmRunGC(pVM, pVCpu);
STAM_PROFILE_STOP(&pVCpu->em.s.StatHmExec, x);
}
else
{
/* Give up this time slice; virtual time continues */
STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
RTThreadSleep(5);
STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
rc = VINF_SUCCESS;
}
/*
* Deal with high priority post execution FFs before doing anything else.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
/*
* Process the returned status code.
*/
if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
break;
rc = emR3HmHandleRC(pVM, pVCpu, pCtx, rc);
if (rc != VINF_SUCCESS)
break;
/*
* Check and execute forced actions.
*/
#ifdef VBOX_HIGH_RES_TIMERS_HACK
TMTimerPollVoid(pVM, pVCpu);
#endif
if ( VM_FF_IS_PENDING(pVM, VM_FF_ALL_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_ALL_MASK))
{
rc = emR3ForcedActions(pVM, pVCpu, rc);
VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
if ( rc != VINF_SUCCESS
&& rc != VINF_EM_RESCHEDULE_HM)
{
*pfFFDone = true;
break;
}
}
}
/*
* Return to outer loop.
*/
#if defined(LOG_ENABLED) && defined(DEBUG)
RTLogFlush(NULL);
#endif
return rc;
}
/**
* The global 1 halt method - Block in GMM (ring-0) and let it
* try take care of the global scheduling of EMT threads.
*/
static DECLCALLBACK(int) vmR3HaltGlobal1Halt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t u64Now)
{
PUVM pUVM = pUVCpu->pUVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
PVM pVM = pUVCpu->pVM;
Assert(VMMGetCpu(pVM) == pVCpu);
NOREF(u64Now);
/*
* Halt loop.
*/
//uint64_t u64NowLog, u64Start;
//u64Start = u64NowLog = RTTimeNanoTS();
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
unsigned cLoops = 0;
for (;; cLoops++)
{
/*
* Work the timers and check if we can exit.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
/*
* Estimate time left to the next event.
*/
//u64NowLog = RTTimeNanoTS();
uint64_t u64Delta;
uint64_t u64GipTime = TMTimerPollGIP(pVM, pVCpu, &u64Delta);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
/*
* Block if we're not spinning and the interval isn't all that small.
*/
if (u64Delta >= pUVM->vm.s.Halt.Global1.cNsSpinBlockThresholdCfg)
{
VMMR3YieldStop(pVM);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
//RTLogPrintf("loop=%-3d u64GipTime=%'llu / %'llu now=%'llu / %'llu\n", cLoops, u64GipTime, u64Delta, u64NowLog, u64GipTime - u64NowLog);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_HALT, u64GipTime, NULL);
uint64_t const u64EndSchedHalt = RTTimeNanoTS();
uint64_t const cNsElapsedSchedHalt = u64EndSchedHalt - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
if (rc == VERR_INTERRUPTED)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "vmR3HaltGlobal1Halt: VMMR0_DO_GVMM_SCHED_HALT->%Rrc\n", rc);
break;
}
else
{
int64_t const cNsOverslept = u64EndSchedHalt - u64GipTime;
if (cNsOverslept > 50000)
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockOverslept, cNsOverslept);
else if (cNsOverslept < -50000)
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockInsomnia, cNsElapsedSchedHalt);
else
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockOnTime, cNsElapsedSchedHalt);
}
}
/*
* When spinning call upon the GVMM and do some wakups once
* in a while, it's not like we're actually busy or anything.
*/
else if (!(cLoops & 0x1fff))
{
uint64_t const u64StartSchedYield = RTTimeNanoTS();
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_POLL, false /* don't yield */, NULL);
uint64_t const cNsElapsedSchedYield = RTTimeNanoTS() - u64StartSchedYield;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltYield, cNsElapsedSchedYield);
}
}
//RTLogPrintf("*** %u loops %'llu; lag=%RU64\n", cLoops, u64NowLog - u64Start, TMVirtualSyncGetLag(pVM));
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Method 1 - Block whenever possible, and when lagging behind
* switch to spinning for 10-30ms with occasional blocking until
* the lag has been eliminated.
*/
static DECLCALLBACK(int) vmR3HaltMethod1Halt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t u64Now)
{
PUVM pUVM = pUVCpu->pUVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
PVM pVM = pUVCpu->pVM;
/*
* To simplify things, we decide up-front whether we should switch to spinning or
* not. This makes some ASSUMPTIONS about the cause of the spinning (PIT/RTC/PCNet)
* and that it will generate interrupts or other events that will cause us to exit
* the halt loop.
*/
bool fBlockOnce = false;
bool fSpinning = false;
uint32_t u32CatchUpPct = TMVirtualSyncGetCatchUpPct(pVM);
if (u32CatchUpPct /* non-zero if catching up */)
{
if (pUVCpu->vm.s.Halt.Method12.u64StartSpinTS)
{
fSpinning = TMVirtualSyncGetLag(pVM) >= pUVM->vm.s.Halt.Method12.u32StopSpinningCfg;
if (fSpinning)
{
uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
fBlockOnce = u64Now - pUVCpu->vm.s.Halt.Method12.u64LastBlockTS
> RT_MAX(pUVM->vm.s.Halt.Method12.u32MinBlockIntervalCfg,
RT_MIN(u64Lag / pUVM->vm.s.Halt.Method12.u32LagBlockIntervalDivisorCfg,
pUVM->vm.s.Halt.Method12.u32MaxBlockIntervalCfg));
}
else
{
//RTLogRelPrintf("Stopped spinning (%u ms)\n", (u64Now - pUVCpu->vm.s.Halt.Method12.u64StartSpinTS) / 1000000);
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = 0;
}
}
else
{
fSpinning = TMVirtualSyncGetLag(pVM) >= pUVM->vm.s.Halt.Method12.u32StartSpinningCfg;
if (fSpinning)
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = u64Now;
}
}
else if (pUVCpu->vm.s.Halt.Method12.u64StartSpinTS)
{
//RTLogRelPrintf("Stopped spinning (%u ms)\n", (u64Now - pUVCpu->vm.s.Halt.Method12.u64StartSpinTS) / 1000000);
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = 0;
}
/*
* Halt loop.
*/
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
unsigned cLoops = 0;
for (;; cLoops++)
{
/*
* Work the timers and check if we can exit.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
/*
* Estimate time left to the next event.
*/
uint64_t u64NanoTS;
TMTimerPollGIP(pVM, pVCpu, &u64NanoTS);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
/*
* Block if we're not spinning and the interval isn't all that small.
*/
if ( ( !fSpinning
|| fBlockOnce)
#if 1 /* DEBUGGING STUFF - REMOVE LATER */
&& u64NanoTS >= 100000) /* 0.100 ms */
#else
&& u64NanoTS >= 250000) /* 0.250 ms */
#endif
{
const uint64_t Start = pUVCpu->vm.s.Halt.Method12.u64LastBlockTS = RTTimeNanoTS();
VMMR3YieldStop(pVM);
uint32_t cMilliSecs = RT_MIN(u64NanoTS / 1000000, 15);
if (cMilliSecs <= pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg)
cMilliSecs = 1;
else
cMilliSecs -= pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg;
//RTLogRelPrintf("u64NanoTS=%RI64 cLoops=%3d sleep %02dms (%7RU64) ", u64NanoTS, cLoops, cMilliSecs, u64NanoTS);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, cMilliSecs);
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
/*
* Calc the statistics.
* Update averages every 16th time, and flush parts of the history every 64th time.
*/
const uint64_t Elapsed = RTTimeNanoTS() - Start;
pUVCpu->vm.s.Halt.Method12.cNSBlocked += Elapsed;
if (Elapsed > u64NanoTS)
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong += Elapsed - u64NanoTS;
pUVCpu->vm.s.Halt.Method12.cBlocks++;
if (!(pUVCpu->vm.s.Halt.Method12.cBlocks & 0xf))
{
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg = pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong / pUVCpu->vm.s.Halt.Method12.cBlocks;
if (!(pUVCpu->vm.s.Halt.Method12.cBlocks & 0x3f))
{
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong = pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg * 0x40;
pUVCpu->vm.s.Halt.Method12.cBlocks = 0x40;
}
}
//RTLogRelPrintf(" -> %7RU64 ns / %7RI64 ns delta%s\n", Elapsed, Elapsed - u64NanoTS, fBlockOnce ? " (block once)" : "");
/*
* Clear the block once flag if we actually blocked.
*/
if ( fBlockOnce
&& Elapsed > 100000 /* 0.1 ms */)
fBlockOnce = false;
}
}
//if (fSpinning) RTLogRelPrintf("spun for %RU64 ns %u loops; lag=%RU64 pct=%d\n", RTTimeNanoTS() - u64Now, cLoops, TMVirtualSyncGetLag(pVM), u32CatchUpPct);
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* The old halt loop.
*/
static DECLCALLBACK(int) vmR3HaltOldDoHalt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t /* u64Now*/)
{
/*
* Halt loop.
*/
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
//unsigned cLoops = 0;
for (;;)
{
/*
* Work the timers and check if we can exit.
* The poll call gives us the ticks left to the next event in
* addition to perhaps set an FF.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
uint64_t u64NanoTS;
TMTimerPollGIP(pVM, pVCpu, &u64NanoTS);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
if (u64NanoTS < 50000)
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d spin\n", u64NanoTS, cLoops++);
/* spin */;
}
else
{
VMMR3YieldStop(pVM);
//uint64_t u64Start = RTTimeNanoTS();
if (u64NanoTS < 870000) /* this is a bit speculative... works fine on linux. */
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d yield", u64NanoTS, cLoops++);
uint64_t const u64StartSchedYield = RTTimeNanoTS();
RTThreadYield(); /* this is the best we can do here */
uint64_t const cNsElapsedSchedYield = RTTimeNanoTS() - u64StartSchedYield;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltYield, cNsElapsedSchedYield);
}
else if (u64NanoTS < 2000000)
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d sleep 1ms", u64NanoTS, cLoops++);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1);
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
}
else
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d sleep %dms", u64NanoTS, cLoops++, (uint32_t)RT_MIN((u64NanoTS - 500000) / 1000000, 15));
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, RT_MIN((u64NanoTS - 1000000) / 1000000, 15));
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
}
//uint64_t u64Slept = RTTimeNanoTS() - u64Start;
//RTLogPrintf(" -> rc=%Rrc in %RU64 ns / %RI64 ns delta\n", rc, u64Slept, u64NanoTS - u64Slept);
}
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Halted VM Wait.
* Any external event will unblock the thread.
*
* @returns VINF_SUCCESS unless a fatal error occurred. In the latter
* case an appropriate status code is returned.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param fIgnoreInterrupts If set the VM_FF_INTERRUPT flags is ignored.
* @thread The emulation thread.
* @remarks Made visible for implementing vmsvga sync register.
* @internal
*/
VMMR3_INT_DECL(int) VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, bool fIgnoreInterrupts)
{
LogFlow(("VMR3WaitHalted: fIgnoreInterrupts=%d\n", fIgnoreInterrupts));
/*
* Check Relevant FFs.
*/
const uint32_t fMask = !fIgnoreInterrupts
? VMCPU_FF_EXTERNAL_HALTED_MASK
: VMCPU_FF_EXTERNAL_HALTED_MASK & ~(VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC);
if ( VM_FF_IS_PENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_IS_PENDING(pVCpu, fMask))
{
LogFlow(("VMR3WaitHalted: returns VINF_SUCCESS (FF %#x FFCPU %#x)\n", pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions));
return VINF_SUCCESS;
}
/*
* The yielder is suspended while we're halting, while TM might have clock(s) running
* only at certain times and need to be notified..
*/
if (pVCpu->idCpu == 0)
VMMR3YieldSuspend(pVM);
TMNotifyStartOfHalt(pVCpu);
/*
* Record halt averages for the last second.
*/
PUVMCPU pUVCpu = pVCpu->pUVCpu;
uint64_t u64Now = RTTimeNanoTS();
int64_t off = u64Now - pUVCpu->vm.s.u64HaltsStartTS;
if (off > 1000000000)
{
if (off > _4G || !pUVCpu->vm.s.cHalts)
{
pUVCpu->vm.s.HaltInterval = 1000000000 /* 1 sec */;
pUVCpu->vm.s.HaltFrequency = 1;
}
else
{
pUVCpu->vm.s.HaltInterval = (uint32_t)off / pUVCpu->vm.s.cHalts;
pUVCpu->vm.s.HaltFrequency = ASMMultU64ByU32DivByU32(pUVCpu->vm.s.cHalts, 1000000000, (uint32_t)off);
}
pUVCpu->vm.s.u64HaltsStartTS = u64Now;
pUVCpu->vm.s.cHalts = 0;
}
pUVCpu->vm.s.cHalts++;
/*
* Do the halt.
*/
VMCPU_ASSERT_STATE(pVCpu, VMCPUSTATE_STARTED);
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HALTED);
PUVM pUVM = pUVCpu->pUVM;
int rc = g_aHaltMethods[pUVM->vm.s.iHaltMethod].pfnHalt(pUVCpu, fMask, u64Now);
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
/*
* Notify TM and resume the yielder
*/
TMNotifyEndOfHalt(pVCpu);
if (pVCpu->idCpu == 0)
VMMR3YieldResume(pVM);
LogFlow(("VMR3WaitHalted: returns %Rrc (FF %#x)\n", rc, pVM->fGlobalForcedActions));
return rc;
}
