uint32_t SIZE_OPTIMIZATION EEEWrite(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint32_t size, \
uint8_t* pData)
{
uint32_t ret = FTFx_OK; /* Return code variable */
uint32_t temp; /* variable temp */
/* convert to byte address */
dest = WORD2BYTE(dest);
/* Check if EEE is enabled */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
if(REG_READ(temp) & FTFx_SSD_FCNFG_EEERDY)
{
/* check range */
if((dest < WORD2BYTE(pSSDConfig->EERAMBase)) || \
((dest + size) > (WORD2BYTE(pSSDConfig->EERAMBase) + pSSDConfig->EEESize)))
{
ret = FTFx_ERR_RANGE;
}
while ((size > 0x0U) && (ret == FTFx_OK))
{
/* dest is 32bit-aligned and size is not less than 4 */
if ((!(dest & 0x03U)) && (size >= 0x04U))
{
ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x04U);
}
else if ((!(dest & 0x1U)) && (size >= 0x02U))
{
ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x02U);
}
else
{
ret = WaitEEWriteToFinish(pSSDConfig, &dest, &size, &pData, 0x01U);
}
}
}
else
{
ret = FTFx_ERR_NOEEE;
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
/* Having accumulated a MAC, finish processing and return it */
void
s128_finish(s128_ctx *c, UCHAR *buf, int nbytes)
{
UCHAR *endbuf;
WORD t = 0;
if ((nbytes & 3) != 0)
abort();
/* perturb the state to mark end of input -- sort of like adding more key */
ADDKEY(INITKONST);
cycle(c->R);
XORNL(nltap(c));
s128_diffuse(c);
/* don't bother optimising this loop, because it's a state
* of delusion to generate more than N words of MAC.
*/
endbuf = &buf[nbytes];
while (buf < endbuf)
{
cycle(c->R);
t = nltap(c);
WORD2BYTE(t, buf);
buf += 4;
}
}
/* Reseed the PRNG given by randomStruct.
* It requires previous calls to RandomUpdate. If there is no (enough)
* entropy stored returns PRNG_NO_DATA_TO_RESEED. Use GetRandomBytesNeeded
* to find out how much (random) input is still needed.
*/
u32 RandomReseed (RANDOM_STRUCT *randStruct)
{
u8 auxbuff[PRNG_MOD_BLEN];
if (randStruct == NULL) return PRNG_NOT_INIT;
if (randStruct->bytesPool) {
/* reseed from pool; new_state = H(previous_state || pool) */
/* transform zstate to byte string */
WORD2BYTE (auxbuff, randStruct->zstate, PRNG_MOD_BLEN);
/* compute hash */
SHA1Init (&(randStruct->hashCtx));
SHA1Update (&(randStruct->hashCtx), auxbuff, PRNG_MOD_BLEN);
SHA1Update (&(randStruct->hashCtx),
randStruct->pool, PRNG_MOD_BLEN);
SHA1Final (randStruct->pool, &(randStruct->hashCtx));
/* transform new pool to mpz number (zstate, the new prng state) */
BYTE2WORD (randStruct->zstate, randStruct->pool, PRNG_MOD_BLEN);
return PRNG_NO_ERROR;
}
else
/* no input has been fed since last reseed! */
return PRNG_NO_DATA_TO_RESEED;
}
uint32_t SIZE_OPTIMIZATION PFlashSwapCtl(PFLASH_SSD_CONFIG pSSDConfig,uint32_t addr, uint8_t swapcmd,uint8_t* pCurrentSwapMode, \
uint8_t* pCurrentSwapBlockStatus, \
uint8_t* pNextSwapBlockStatus, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret; /* Return code variable */
uint32_t temp; /* temporary variable */
addr = WORD2BYTE(addr - pSSDConfig->PFlashBase);
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_PFLASH_SWAP);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(addr));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, swapcmd);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, 0xFFU);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
REG_WRITE(temp, 0xFFU);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
REG_WRITE(temp, 0xFFU);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
if (FTFx_OK == ret)
{
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
*pCurrentSwapMode = REG_READ(temp);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
*pCurrentSwapBlockStatus = REG_READ(temp);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB7_OFFSET;
*pNextSwapBlockStatus = REG_READ(temp);
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return (ret);
}
void
s128_decrypt(s128_ctx *c, UCHAR *buf, int nbytes)
{
UCHAR *endbuf;
WORD t = 0;
if ((nbytes & 3) != 0)
abort();
endbuf = &buf[nbytes];
/* do small or odd size buffers the slow way, at least at first */
while ((nbytes % (N*4)) != 0) {
cycle(c->R);
t = nltap(c);
t ^= BYTE2WORD(buf);
macfunc(c, t);
WORD2BYTE(t, buf);
nbytes -= 4;
buf += 4;
}
/* now do lots at a time, if there's any left */
while (buf < endbuf)
{
DROUND(0);
DROUND(1);
DROUND(2);
DROUND(3);
DROUND(4);
DROUND(5);
DROUND(6);
DROUND(7);
DROUND(8);
DROUND(9);
DROUND(10);
DROUND(11);
DROUND(12);
DROUND(13);
DROUND(14);
DROUND(15);
DROUND(16);
buf += 4*17;
}
}
uint32_t SIZE_OPTIMIZATION FlashVerifySection(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint16_t number, \
uint8_t marginLevel, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* convert to byte address */
dest = WORD2BYTE(dest);
/* check if the destination is aligned or not */
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashBlockSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashBlockSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(FTFx_OK == ret)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_VERIFY_SECTION);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB6_OFFSET;
REG_WRITE(temp, marginLevel);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
/*
PSEC-KEM key encapsulation mechanism
Return: TRUE if succeed; otherwise FALSE
*/
u8 PSEC_KEM_KEM(
PSEC_KEM_PUB_KEY *publicKey, /* PSEC_KEM public key */
PSEC_KEM_KEY_ENCAPSULATION *keyEncapsulation, /* returned keyEncapsulation */
PSEC_KEM_KEY_MATERIAL *keyMaterial, /* returned key material */
EC_PARAM *E,
PSEC_KEM_EC_ENCODING_FORMAT format
)
{
mpz_t s, u, res, v;
u8 *s_raw, *u_raw, *t_raw, *mgf_arg_1, *mgf_arg_2, *res_raw, *v_raw, *PEH_raw;
u8 *EG_raw;
s32 i;
u32 hoLen, uoLen, EGoLen, PEHoLen, qoLen;
EC_POINT h_tilde, g_tilde;
mpz_init(s);
mpz_init(u);
mpz_init(res);
mpz_init(v);
hoLen = (publicKey->hLen) >> 3;
uoLen = (u32)ceil(E->pLen/8.0) + 16;
keyMaterial->KoLen = (publicKey->outputKeyLen) >> 3;
qoLen = (u32)ceil(E->qLen/8.0);
if (format == COMPRESSED) {
EGoLen = 1 + qoLen;
PEHoLen = 1 + qoLen;
} else {
EGoLen = 1 + 2*qoLen;
PEHoLen = 1 + 2*qoLen;
}
if ((publicKey->pk).inf_id == EC_O)
PEHoLen = 1;
if ((E->P).inf_id == EC_O)
EGoLen = 1;
#ifdef DEBUG
printf("hoLen = %u\n", hoLen);
printf("uoLen = %u\n", uoLen);
printf("keyMaterial->KoLen = %u\n", keyMaterial->KoLen);
printf("EGoLen = %u\n", EGoLen);
printf("PEHoLen = %u\n", PEHoLen);
#endif
EC_initPoint ( &h_tilde );
EC_initPoint ( &g_tilde);
s_raw = (BYTE *) malloc (hoLen);
u_raw = (BYTE *) malloc (uoLen);
t_raw = (BYTE *) malloc (uoLen + keyMaterial->KoLen);
mgf_arg_1 = (u8 *) malloc (4 + hoLen);
mgf_arg_2 = (u8 *) malloc (4 + EGoLen + PEHoLen);
res_raw = (u8 *) malloc (hoLen);
v_raw = (u8 *) malloc (hoLen);
PEH_raw = (u8 *) malloc (PEHoLen);
EG_raw = (u8 *) malloc (EGoLen);
/* generate s */
GenerateBytes(s_raw, hoLen, global_prng);
BYTE2WORD (s, s_raw, hoLen);
#ifdef DEBUG
printf("s = 0x%s\n", mpz_get_str(NULL, 16, s));
printf("\n"); fflush(stdout);
#endif
/* compute t = MGF1(0 || s) */
U32TO8_BIG(mgf_arg_1, 0L);
memcpy(mgf_arg_1+4, s_raw, hoLen);
MGF1( t_raw, 8 * (uoLen + keyMaterial->KoLen), mgf_arg_1, 4 + hoLen);
#ifdef DEBUG
printf("t = ");
printAsHex(t_raw, uoLen+keyMaterial->KoLen);
printf("\n"); fflush(stdout);
#endif
/* parse t as t = u || K */
memcpy( u_raw, t_raw, uoLen );
BYTE2WORD( u, u_raw, uoLen );
memcpy( keyMaterial->K_raw, t_raw+uoLen, keyMaterial->KoLen );
#ifdef DEBUG
printf("u = 0x%s\n", mpz_get_str(NULL, 16, u));
printf("keyMaterial = ");
printAsHex(keyMaterial->K_raw, keyMaterial->KoLen);
printf("\n"); fflush(stdout);
#endif
/* compute h_tilde = u * publicKey->pk */
EC_Mult( &h_tilde, u, &(publicKey->pk), E );
ec2os (PEH_raw, &h_tilde, E, format);
#ifdef DEBUG
printf("h_tilde.x = 0x%s\n", mpz_get_str(NULL, 16, h_tilde.x));
printf("h_tilde.y = 0x%s\n", mpz_get_str(NULL, 16, h_tilde.y));
printf("PEH = ");
printAsHex(PEH_raw, PEHoLen);
printf("\n"); fflush(stdout);
#endif
/* compute g_tilde = u * E->P */
EC_Mult( &g_tilde, u, &(E->P), E );
#ifdef DEBUG
printf("g_tilde.x = 0x%s\n", mpz_get_str(NULL, 16, g_tilde.x));
printf("g_tilde.y = 0x%s\n", mpz_get_str(NULL, 16, g_tilde.y));
printf("g_tilde.inf_id = %u\n", g_tilde.inf_id);
#endif
/* convert g_tilde's EC point to an octet string according to P1363 E.2.3.2 */
ec2os( EG_raw, &g_tilde, E, format);
#ifdef DEBUG
printf("EG = ");
printAsHex(EG_raw, EGoLen);
printf("\n"); fflush(stdout);
#endif
/* compute res = MGF1( 1 || EG || PEH ) */
U32TO8_BIG ( mgf_arg_2, 1L );
memcpy( mgf_arg_2 + 4, EG_raw, EGoLen );
memcpy( mgf_arg_2 + 4 + EGoLen, PEH_raw, PEHoLen );
MGF1( res_raw, publicKey->hLen, mgf_arg_2, 4 + EGoLen + PEHoLen);
BYTE2WORD( res, res_raw, hoLen);
#ifdef DEBUG
printf("res = 0x%s\n", mpz_get_str(NULL, 16, res));
printf("\n"); fflush(stdout);
#endif
/* compute v = s \xor res */
mpz_xor(v, s, res);
WORD2BYTE(v_raw, v, hoLen);
#ifdef DEBUG
printf("v = 0x%s\n", mpz_get_str(NULL, 16, v));
printf("\n"); fflush(stdout);
#endif
/* output C0 = EG || v */
memcpy( keyEncapsulation->C0, EG_raw, EGoLen);
memcpy( keyEncapsulation->C0 + EGoLen, v_raw, hoLen);
#ifdef DEBUG
printf("C0 = ");
printAsHex(keyEncapsulation->C0, keyEncapsulation->C0oLen);
printf("\n"); fflush(stdout);
#endif
/* clean up */
mpz_clear(s);
mpz_clear(u);
mpz_clear(res);
mpz_clear(v);
memset(s_raw, 0, hoLen);
memset(u_raw, 0, uoLen);
memset(t_raw, 0, uoLen + keyMaterial->KoLen);
memset(mgf_arg_1, 0, 4+hoLen);
memset(mgf_arg_2, 0, 4 + EGoLen + PEHoLen);
memset(res_raw, 0, hoLen);
memset(v_raw, 0, hoLen);
memset(PEH_raw, 0, PEHoLen);
memset(EG_raw, 0, EGoLen);
free(s_raw);
free(u_raw);
free(t_raw);
free(mgf_arg_1);
free(mgf_arg_2);
free(res_raw);
free(v_raw);
free(PEH_raw);
free(EG_raw);
EC_clearPoint ( &h_tilde );
EC_clearPoint ( &g_tilde );
return TRUE;
}
/****************************************************************************
*
* Function Name : FlashEraseSector
* Description : Perform erase operation on Flash
* Arguments : PFLASH_SSD_CONFIG, UINT32, UINT32, pFLASHCOMMANDSEQUENCE
* Return Value : UINT32
*
*****************************************************************************/
UINT32 FlashEraseSector(PFLASH_SSD_CONFIG pSSDConfig, \
UINT32 dest, \
UINT32 size, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
UINT32 ret; /* return code variable */
UINT32 sectorSize ,temp; /* size of one sector */
ret = FTFx_OK;
/* convert to byte address */
dest = WORD2BYTE(dest);
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashBlockSize)))
{
dest = dest - temp + 0x800000;
sectorSize = FTFx_DSECTOR_SIZE;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBlockBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashBlockSize)))
{
dest -= temp;
sectorSize = FTFx_PSECTOR_SIZE;
}else{
ret = FTFx_ERR_ACCERR;
goto EXIT;
}
}
/* check if the size is sector alignment or not */
if(size & (sectorSize-1))
{
/* return an error code FTFx_ERR_SIZE */
ret = FTFx_ERR_SIZE;
goto EXIT;
}
while(size > 0)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear*/
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET,FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET, FTFx_ERASE_SECTOR);
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET, GET_BIT_16_23(dest));
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET, GET_BIT_8_15(dest));
REG_WRITE(pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET, GET_BIT_0_7(dest));
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
/* checking the success of command execution */
if(FTFx_OK != ret)
{
break;
}
else
{
/* update size and destination address */
size -= sectorSize;
dest += sectorSize;
}
}
EXIT:
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
return(ret);
}
uint32_t SIZE_OPTIMIZATION FlashReadResource(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint8_t* pDataArray, \
uint8_t resourceSelectCode, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint8_t i;
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* convert to byte address */
dest = WORD2BYTE(dest);
/* check if the destination is aligned or not */
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(ret == FTFx_OK)
{
/* clear RDCOLERR & ACCERR & FPVIOL flag in flash status register. Write 1 to clear */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to the command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_READ_RESOURCE);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + RSRC_CODE_OFSSET;
REG_WRITE(temp, resourceSelectCode);
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
if (FTFx_OK == ret)
{
/* Read the data from the FCCOB registers into the pDataArray */
for (i = 0x0U; i < PGM_SIZE_BYTE; i ++)
{
temp = pSSDConfig->ftfxRegBase + i + 0x08U;
pDataArray[i] = REG_READ(temp);
}
}
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
uint32_t SIZE_OPTIMIZATION FlashProgramSection(PFLASH_SSD_CONFIG pSSDConfig, \
uint32_t dest, \
uint16_t number, \
pFLASHCOMMANDSEQUENCE pFlashCommandSequence)
{
uint32_t ret = FTFx_OK; /* return code variable */
uint32_t temp;
/* check RAMRDY bit of the flash configuration register */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCNFG_OFFSET;
if(0x0U == (REG_BIT_GET(temp, FTFx_SSD_FCNFG_RAMRDY)))
{
/* return an error code FTFx_ERR_RAMRDY */
ret = FTFx_ERR_RAMRDY;
}
else
{
/* convert to byte address */
dest = WORD2BYTE(dest);
#if (DEBLOCK_SIZE)
temp = WORD2BYTE(pSSDConfig->DFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->DFlashSize)))
{
dest = dest - temp + 0x800000U;
}
else
#endif
{
temp = WORD2BYTE(pSSDConfig->PFlashBase);
if((dest >= temp) && (dest < (temp + pSSDConfig->PFlashSize)))
{
dest -= temp;
}
else
{
ret = FTFx_ERR_ACCERR;
}
}
if(ret == FTFx_OK)
{
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FSTAT_OFFSET;
REG_WRITE(temp, FTFx_SSD_FSTAT_ERROR_BITS);
/* passing parameter to command */
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB0_OFFSET;
REG_WRITE(temp, FTFx_PROGRAM_SECTION);
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB1_OFFSET;
REG_WRITE(temp, GET_BIT_16_23(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB2_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB3_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(dest));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB4_OFFSET;
REG_WRITE(temp, GET_BIT_8_15(number));
temp = pSSDConfig->ftfxRegBase + FTFx_SSD_FCCOB5_OFFSET;
REG_WRITE(temp, GET_BIT_0_7(number));
/* calling flash command sequence function to execute the command */
ret = pFlashCommandSequence(pSSDConfig);
}
}
#if C90TFS_ENABLE_DEBUG
/* Enter Debug state if enabled */
if (TRUE == (pSSDConfig->DebugEnable))
{
ENTER_DEBUG_MODE;
}
#endif
return(ret);
}
u32 GenerateBytes (
u8 *block,
u32 blockLen,
RANDOM_STRUCT *randStruct
)
{
u32 available;
u8 auxbuff[PRNG_MOD_BLEN];
mpz_t zaux;
u32 return_code = PRNG_NO_ERROR;
if (randStruct == NULL) return PRNG_NOT_INIT;
/* Is the prng seeded? */
if (randStruct->bytesNeeded) return PRNG_NOT_SEEDED;
/* Initializations */
mpz_init_set_ui (zaux, 0L);
if (!randStruct->maxNoOutputBlocks)
{
/* max no. of output blocks exceeded; we need to reseed */
return_code = RandomReseed (randStruct);
/* If return_code is PRNG_NO_DATA_TO_RESEED, return output anyway
* but forward return code */
} else
randStruct->maxNoOutputBlocks--;
/* There may be output available from previous output generation */
available = randStruct->outputAvailable;
/* Generate and copy prng output */
while (blockLen > available) {
/* copy prng output (if any) to user buffer */
memcpy ((u8 *)block,
(u8 *)&randStruct->output[SHA1_DIGESTSIZE-available], available);
block += available;
blockLen -= available;
/*
* generate new output
*/
/* In FIPS 186 apdx 3.1, prng output is G(state + optional_user_input)
* Here, optional_user_input = 0.
* To avoid Blaichenbacher's attack, there is NO reduction modulo q
* on the output. */
/* transform prng state (zstate) into byte array */
WORD2BYTE (auxbuff, randStruct->zstate, PRNG_MOD_BLEN);
/* Compute randStruct->output = G(state); */
sha1G (randStruct, auxbuff);
/* randStruct->output now contains the PRNG output */
available = SHA1_DIGESTSIZE;
/*
* update prng state
*/
/* transform output into mpz_t number */
BYTE2WORD (zaux, randStruct->output, SHA1_DIGESTSIZE);
/* update state: new state S_{i+1} = H(Si+ti) + S_i + 1 */
mpz_add (zaux, zaux, randStruct->zstate);
mpz_add (randStruct->zstate, zaux, one);
mpz_mod (randStruct->zstate, randStruct->zstate, two2pow);
}
/* copy last chunk of prng output to user buffer */
memcpy ((u8 *)block,
(u8 *)&randStruct->output[SHA1_DIGESTSIZE-available], blockLen);
randStruct->outputAvailable = available - blockLen;
/* Zeroize sensitive information */
memset (auxbuff, 0, PRNG_MOD_BLEN);
mpz_clear (zaux);
available = 0;
return (return_code);
}
