static int efuse_ioctl( struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg )
{
switch (cmd)
{
case EFUSE_ENCRYPT_ENABLE:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_ON,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_DISABLE:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_OFF,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_RESET:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_RESET_ON,
CNTL4_ENCRYPT_RESET_BIT, CNTL4_ENCRYPT_RESET_SIZE);
break;
default:
return -ENOTTY;
}
return 0;
}
static void init_vdin(int width, int format)
{
WRITE_MPEG_REG(PERIPHS_PIN_MUX_0, READ_MPEG_REG(PERIPHS_PIN_MUX_0)|
((1 << 10) | // pm_gpioA_lcd_in_de
(1 << 9) | // pm_gpioA_lcd_in_vs
(1 << 8) | // pm_gpioA_lcd_in_hs
(1 << 7) | // pm_gpioA_lcd_in_clk
(1 << 6))); // pm_gpioA_lcd_in
WRITE_MPEG_REG_BITS(VDIN_ASFIFO_CTRL2, 0x39, 2, 6);
//if(format==TVIN_SIG_FMT_HDMI_1440x480I_60Hz){
if(width == 1440){
// ratio
WRITE_CBUS_REG_BITS(VDIN_ASFIFO_CTRL2, 1, 16, 4);
// en
WRITE_CBUS_REG_BITS(VDIN_ASFIFO_CTRL2, 1, 24, 1);
// manual reset, rst = 1 & 0
WRITE_CBUS_REG_BITS(VDIN_ASFIFO_CTRL2, 1, 25, 1);
WRITE_CBUS_REG_BITS(VDIN_ASFIFO_CTRL2, 0, 25, 1);
// output_width_m1
WRITE_MPEG_REG(VDIN_INTF_WIDTHM1, width/2 - 1);
}
else{
WRITE_MPEG_REG_BITS(VDIN_ASFIFO_CTRL2, 0, 16, 10);
WRITE_MPEG_REG(VDIN_INTF_WIDTHM1, width - 1);
}
//vdin0_select_in(6, 2, 1, 0, 0, width);
//vdin0_set_matrix_rgb2ycbcr(0);
}
static void aml_8726m_set_bl_level(unsigned level)
{
unsigned cs_level,pwm_level,low,hi;
bl_level = level;
level = level*179/255;
if(level>=120){ //120 - 179
cs_level = 9 -(level - 120)/15;
pwm_level = 85 + (level - 120)%15;
}
else if(level>=20){ //20 - 119
cs_level = 13 - (level -20)/25;
pwm_level = 75 + (level - 20)%25;
}
else{ // <20
cs_level = 13;
pwm_level = 0;
}
hi = (BL_MAX_LEVEL/100)*pwm_level;
low = BL_MAX_LEVEL - hi;
WRITE_CBUS_REG_BITS(VGHL_PWM_REG0, cs_level, 0, 4);
//SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31));
SET_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0));
WRITE_CBUS_REG_BITS(PWM_PWM_A,low,0,16); //low
WRITE_CBUS_REG_BITS(PWM_PWM_A,hi,16,16); //hi
}
static int efuse_ioctl( struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg )
{
switch (cmd)
{
case EFUSE_ENCRYPT_ENABLE:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_ON,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_DISABLE:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_ENABLE_OFF,
CNTL4_ENCRYPT_ENABLE_BIT, CNTL4_ENCRYPT_ENABLE_SIZE);
break;
case EFUSE_ENCRYPT_RESET:
WRITE_CBUS_REG_BITS( EFUSE_CNTL4, CNTL4_ENCRYPT_RESET_ON,
CNTL4_ENCRYPT_RESET_BIT, CNTL4_ENCRYPT_RESET_SIZE);
break;
case EFUSE_INFO_GET:
{
efuseinfo_item_t *info = (efuseinfo_item_t*)arg;
if(efuse_getinfo_byID(info->id, info) < 0)
return -EFAULT;
}
break;
default:
return -ENOTTY;
}
return 0;
}
static void init_pwm(void)
{
int pwm_level = 24000000/irreceiver_data->freq/2;
unsigned int pwmReg = 0;
int idx = irreceiver_data->pwm_no;
if(PWM_A == idx)
{
pwmReg = PWM_PWM_A;
}
else if(PWM_B == idx)
{
pwmReg = PWM_PWM_B;
}
else if(PWM_C == idx)
{
pwmReg = PWM_PWM_C;
}
else if(PWM_D == idx)
{
pwmReg = PWM_PWM_D;
}
close_pwm(irreceiver_data->pwm_no);
irreceiver_data->init_pwm_pinmux();
WRITE_CBUS_REG_BITS(pwmReg, pwm_level, 0, 16); //low
WRITE_CBUS_REG_BITS(pwmReg, pwm_level, 16, 16); //hi
}
static void vdin_hw_powerdown(unsigned int offset)
{
//set VDIN_MEAS_CLK_CNTL, select XTAL clock
WRITE_CBUS_REG((VDIN_MEAS_CLK_CNTL + offset), 0x00000000);
/* disable video data input */
// [ 4] top.datapath_en = 0
WRITE_CBUS_REG_BITS((VDIN_COM_CTRL0 + offset), 0, 4, 1);
/* mux null input */
// [ 3: 0] top.mux = 0/(null, mpeg, 656, tvfe, cvd2, hdmi, dvin)
WRITE_CBUS_REG_BITS((VDIN_COM_CTRL0 + offset), 0, 0, 4);
/* disable clock of blackbar, histogram, histogram, line fifo1, matrix,
* hscaler, pre hscaler, clock0
*/
// [15:14] Disable blackbar clock = 01/(auto, off, on, on)
// [13:12] Disable histogram clock = 01/(auto, off, on, on)
// [11:10] Disable line fifo1 clock = 01/(auto, off, on, on)
// [ 9: 8] Disable matrix clock = 01/(auto, off, on, on)
// [ 7: 6] Disable hscaler clock = 01/(auto, off, on, on)
// [ 5: 4] Disable pre hscaler clock = 01/(auto, off, on, on)
// [ 3: 2] Disable clock0 = 01/(auto, off, on, on)
// [ 0] Enable register clock = 00/(auto, off!!!!!!!!)
WRITE_CBUS_REG((VDIN_COM_GCLK_CTRL + offset), 0x5554);
}
static void __init LED_PWM_REG0_init(void)
{
#if 1 // PWM_C
printk(KERN_INFO "LED_PWM_REG0_init.\n");
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2,(1<<2));
WRITE_CBUS_REG(PWM_PWM_C, (0xff00<<16) |(0xff00<<0));
WRITE_CBUS_REG(PWM_MISC_REG_CD, (1<<0) // enable
|(0<<4) // PWM_A_CLK_SEL: 0:XTAL; 1:ddr_pll_clk; 2:clk81; 3:sys_pll_clk;
|(0x7f<<8) // PWM_A_CLK_DIV
|(1<<15) // PWM_A_CLK_EN
);
#else
// Enable VBG_EN
WRITE_CBUS_REG_BITS(PREG_AM_ANALOG_ADDR, 1, 0, 1);
// wire pm_gpioA_7_led_pwm = pin_mux_reg0[22];
WRITE_CBUS_REG(LED_PWM_REG0,(0 << 31) | // disable the overall circuit
(0 << 30) | // 1:Closed Loop 0:Open Loop
(0 << 16) | // PWM total count
(0 << 13) | // Enable
(1 << 12) | // enable
(0 << 10) | // test
(7 << 7) | // CS0 REF, Voltage FeedBack: about 0.505V
(7 << 4) | // CS1 REF, Current FeedBack: about 0.505V
READ_CBUS_REG(LED_PWM_REG0)&0x0f); // DIMCTL Analog dimmer
WRITE_CBUS_REG_BITS(LED_PWM_REG0,1,0,4); //adust cpu1.2v to 1.26V
#endif
}
static void set_clk_final_div(unsigned div)
{
if(div == 0)
div = 1;
WRITE_CBUS_REG_BITS(HHI_VID_CLK_CNTL, 1, 19, 1);
WRITE_CBUS_REG_BITS(HHI_VID_CLK_CNTL, 0, 16, 3);
WRITE_CBUS_REG_BITS(HHI_VID_CLK_DIV, div-1, 0, 8);
WRITE_CBUS_REG_BITS(HHI_VID_CLK_CNTL, 7, 0, 3);
}
static void init_pwm_d(void)
{
CLEAR_CBUS_REG_MASK(PWM_MISC_REG_CD, (1 << 1));//close PWM_D by default
msleep(100);
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<3));
msleep(100);
WRITE_CBUS_REG_BITS(PWM_PWM_D, pwm_level, 0, 16); //low
WRITE_CBUS_REG_BITS(PWM_PWM_D, pwm_level, 16, 16); //hi
}
static void aml_8726m_bl_init(void)
{
#if 0
unsigned val;
WRITE_CBUS_REG_BITS(PERIPHS_PIN_MUX_0, 0, 22, 1);
WRITE_CBUS_REG_BITS(PREG_AM_ANALOG_ADDR, 1, 0, 1);
WRITE_CBUS_REG(VGHL_PWM_REG0, 0);
WRITE_CBUS_REG(VGHL_PWM_REG1, 0);
WRITE_CBUS_REG(VGHL_PWM_REG2, 0);
WRITE_CBUS_REG(VGHL_PWM_REG3, 0);
WRITE_CBUS_REG(VGHL_PWM_REG4, 0);
val = (0 << 31) | // disable the overall circuit
(0 << 30) | // 1:Closed Loop 0:Open Loop
(PWM_TCNT << 16) | // PWM total count
(0 << 13) | // Enable
(1 << 12) | // enable
(0 << 10) | // test
(3 << 7) | // CS0 REF, Voltage FeedBack: about 0.27V
(7 << 4) | // CS1 REF, Current FeedBack: about 0.54V
(0 << 0); // DIMCTL Analog dimmer
WRITE_CBUS_REG(VGHL_PWM_REG0, val);
val = (1 << 30) | // enable high frequency clock
(PWM_MAX_VAL << 16) | // MAX PWM value
(0 << 0); // MIN PWM value
WRITE_CBUS_REG(VGHL_PWM_REG1, val);
val = (0 << 31) | // disable timeout test mode
(0 << 30) | // timeout based on the comparator output
(0 << 16) | // timeout = 10uS
(0 << 13) | // Select oscillator as the clock (just for grins)
(1 << 11) | // 1:Enable OverCurrent Portection 0:Disable
(3 << 8) | // Filter: shift every 3 ticks
(0 << 6) | // Filter: count 1uS ticks
(0 << 5) | // PWM polarity : negative
(0 << 4) | // comparator: negative, Different with NikeD3
(1 << 0); // +/- 1
WRITE_CBUS_REG(VGHL_PWM_REG2, val);
val = ( 1 << 16) | // Feedback down-sampling = PWM_freq/1 = PWM_freq
( 1 << 14) | // enable to re-write MATCH_VAL
( 210 << 0) ; // preset PWM_duty = 50%
WRITE_CBUS_REG(VGHL_PWM_REG3, val);
val = ( 0 << 30) | // 1:Digital Dimmer 0:Analog Dimmer
( 2 << 28) | // dimmer_timebase = 1uS
(1000 << 14) | // Digital dimmer_duty = 0%, the most darkness
(1000 << 0) ; // dimmer_freq = 1KHz
WRITE_CBUS_REG(VGHL_PWM_REG4, val);
#else
SET_CBUS_REG_MASK(PWM_MISC_REG_AB, (1 << 0));
msleep(100);
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<31));
msleep(100);
#endif
//printk("\n\nBacklight init.\n\n");
}
void set_backlight_level(unsigned level)
{
level = level>BL_MAX_LEVEL ? BL_MAX_LEVEL:(level<BL_MIN_LEVEL ? BL_MIN_LEVEL:level);
#if (BL_CTL==BL_CTL_GPIO)
level = level * 15 / BL_MAX_LEVEL;
level = 15 - level;
WRITE_CBUS_REG_BITS(LED_PWM_REG0, level, 0, 4);
#elif (BL_CTL==BL_CTL_PWM)
level = level * PWM_MAX / BL_MAX_LEVEL ;
WRITE_CBUS_REG_BITS(PWM_PWM_D, (PWM_MAX - level), 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_D, level, 16, 16); //pwm high
#endif
}
static void init_pwm_a(void)
{
CLEAR_CBUS_REG_MASK(PWM_MISC_REG_AB, ((1<<15)|(0<<8)|(1<<0)));//close PWM_A by default
msleep(100);
//GPIOC_0
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0, (1<<21));//dis VGA_HS
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_1, (1<<27));// dis VGHL_PWM
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<0));// enable pwma
msleep(100);
WRITE_CBUS_REG_BITS(PWM_PWM_A, pwm_level, 0, 16); //low
WRITE_CBUS_REG_BITS(PWM_PWM_A, pwm_level, 16, 16); //hi
}
void power_off_backlight(void)
{
//BL_EN: GPIOD_1(PWM_D)
#if (BL_CTL==BL_CTL_GPIO)
WRITE_MPEG_REG(0x2013, READ_MPEG_REG(0x2013) & ~(1 << 17));
#elif (BL_CTL==BL_CTL_PWM)
WRITE_CBUS_REG_BITS(PWM_PWM_D, PWM_MAX, 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_D, 0, 16, 16); //pwm high
CLEAR_CBUS_REG_MASK(PWM_MISC_REG_CD, ((1 << 23) | (1<<1))); //disable pwm clk & pwm output
#endif
msleep(20);
lvds_port_disable();
msleep(20);
}
int lowlevel_init(void)
{
unsigned por_cfg = READ_CBUS_REG(ASSIST_POR_CONFIG);
if (((por_cfg & POR_ROM_BOOT_ENABLE) == 0)) {
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_ROM_BOOT_ENABLE | POR_INTL_SPI;
romboot_info->boot_id = 0;
}
WRITE_CBUS_REG(PAD_PULL_UP_REG0,-1);
WRITE_CBUS_REG(PAD_PULL_UP_REG1,-1);
WRITE_CBUS_REG(PAD_PULL_UP_REG2,-1);
WRITE_CBUS_REG(PAD_PULL_UP_REG3,-1);
//changed by Elvis, add uart rx pull up
//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) ); // Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
pll_initial(); //running under default freq now . Before we fixed the PLL stable problem
unsigned clk;
if ((readl(P_HHI_MPEG_CLK_CNTL) & (1 << 8)) == 0) {
clk = CONFIG_CRYSTAL_MHZ * 1000000;
} else {
clk = romboot_info->clk81;
}
unsigned memory_size;
memory_size = PHYS_MEMORY_SIZE;
serial_init_with_clk(clk);
writel((1<<22)|1000000,P_WATCHDOG_TC);
do {
unsigned ret1, ret2, ret3, ret4;
ret1 = ret2 = ret3 = ret4 = 0;
por_cfg = 0;
ret1 = initial_ddr(&__hw_setting.ddr, __hw_setting.ddr.lane);
display_error(ret1, "DDr Init");
#ifdef CONFIG_MEM_TEST
ret2=memTestDevice((volatile datum *)PHYS_MEMORY_START,memory_size);
display_error(ret2,"TestDevice");
por_cfg=ret2;
#endif
ret3 = memTestDataBus((volatile datum *) PHYS_MEMORY_START);
display_error(ret3, "TestDataBus");
ret4 = memTestAddressBus((volatile datum *) PHYS_MEMORY_START,
memory_size);
display_error(ret4, "TestAddressBus");
por_cfg = ret1 | ret2 | ret3 | ret4;
} while (por_cfg != 0);
writel(0,P_WATCHDOG_RESET);
return 0;
}
void clk_switch(int flag)
{
int i;
if (flag) {
for (i = CLK_COUNT - 1; i >= 0; i--) {
if (clk_flag[i]) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
WRITE_CBUS_REG_BITS(clks[i], clk_flag[i], 19, 2);
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
udelay(1000);
SET_CBUS_REG_MASK(clks[i], (1 << 8)); // normal
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
} else {
SET_CBUS_REG_MASK(clks[i], (1 << 8));
}
clk_flag[i] = 0;
printf("clk %s(%x) on\n", clks_name[i], clks[i]);
}
}
} else {
for (i = 0; i < CLK_COUNT; i++) {
if ((clks[i] == HHI_VID_CLK_CNTL)||(clks[i] == HHI_VIID_CLK_CNTL)) {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 19, 2);
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1<<19)|(1<<20));
}
} else if (clks[i] == HHI_MPEG_CLK_CNTL) {
if (READ_CBUS_REG(clks[i]) & (1 << 8)) {
clk_flag[i] = 1;
udelay(1000);
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8)); // 24M
CLEAR_CBUS_REG_MASK(UART0_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART0_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_CBUS_REG_MASK(UART1_CONTROL, (1 << 19) | 0xFFF);
SET_CBUS_REG_MASK(UART1_CONTROL, (((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff));
CLEAR_AOBUS_REG_MASK(AO_UART_CONTROL, (1 << 19) | 0xFFF);
WRITE_AOBUS_REG_BITS(AO_UART_CONTROL, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0xfff, 0, 12);
}
} else {
clk_flag[i] = READ_CBUS_REG_BITS(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
CLEAR_CBUS_REG_MASK(clks[i], (1 << 8));
}
}
if (clk_flag[i]) {
printf("clk %s(%x) off\n", clks_name[i], clks[i]);
}
}
}
}
// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, viu_type_e viu_type_sel)
{
if((viu_channel_sel > 2) || (viu_channel_sel == 0))
return -1;
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", READ_CBUS_REG(VPU_VIU_VENC_MUX_CTRL));
if(viu_channel_sel == 1){
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
printk("viu chan = 1\n");
}
else{
//viu_channel_sel ==2
WRITE_CBUS_REG_BITS(VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
printk("viu chan = 2\n");
}
printk("VPU_VIU_VENC_MUX_CTRL: 0x%x\n", READ_CBUS_REG(VPU_VIU_VENC_MUX_CTRL));
return 0;
}
void lowlevel_init(void* cur,void * target)
{
int i;
//close ddr
//gpiob_8
clrbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
clrbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//clrbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
//Adjust 1us timer base
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
//vcc_12v/24v power on GPIOX_70
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//backlight GPIOX_53
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
//serial_put_dword(get_timer(0));
//serial_put_dword(readl(0xc1100000+0x200b*4));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
#if 1
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test()){
writel(0,P_WATCHDOG_TC);//disable Watchdog
debug_rom(__FILE__,__LINE__);
}
#else
do{
}while(ddr_init_test(0x6));
#endif
#endif
writel(0,P_WATCHDOG_TC);//disable Watchdog
// serial_puts("\nM2C Systemp Started\n");
}
static void m3ref_lcd_set_brightness(unsigned level)
{
m3ref_lcd_brightness = level;
printk(KERN_DEBUG "%s() brightness=%d\n", __FUNCTION__, m3ref_lcd_brightness);
level = (level > BL_MAX_LEVEL ? BL_MAX_LEVEL
: (level < BL_MIN_LEVEL ? BL_MIN_LEVEL : level));
#if (BL_CTL==BL_CTL_GPIO)
level = level * 15 / BL_MAX_LEVEL;
level = 15 - level;
WRITE_CBUS_REG_BITS(LED_PWM_REG0, level, 0, 4);
#elif (BL_CTL==BL_CTL_PWM)
level = level * PWM_MAX / BL_MAX_LEVEL ;
WRITE_CBUS_REG_BITS(PWM_PWM_D, (PWM_MAX - level), 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_D, level, 16, 16); //pwm high
#endif
}
void aml_8726m_set_bl_level(unsigned level)
{
unsigned high, low;
if (level > 255)
level = 255;
//Analog pwm
high = level*4;
low = ANALOG_BL_MAX_LEVEL - high;
WRITE_CBUS_REG_BITS(PWM_PWM_B, low, 0, 16);
WRITE_CBUS_REG_BITS(PWM_PWM_B, high, 16, 16);
//Digital pwm
WRITE_CBUS_REG(OEH_VE_ADDR, (int)((level*TCON_PWM_VS2)/255));
WRITE_CBUS_REG(CPV1_VE_ADDR, TCON_PWM_VS2 + (int)((level*TCON_PWM_VS2)/255));
WRITE_CBUS_REG(OEV1_VE_ADDR, TCON_PWM_VS3 + (int)((level*TCON_PWM_VS2)/255));
}
void set_backlight_level(unsigned level)
{
//printk("set_backlight_level %d\n", level);
level = level>BL_MAX_LEVEL ? BL_MAX_LEVEL:(level<BL_MIN_LEVEL ? BL_MIN_LEVEL:level);
#if (BL_CTL==BL_CTL_GPIO)
if (level == BL_MIN_LEVEL){
level = 15;
}
else {
level = level * 10 / BL_MAX_LEVEL;
level = 13 - level;
}
WRITE_CBUS_REG_BITS(LED_PWM_REG0, level, 0, 4); // [3-13] 10 level
#elif (BL_CTL==BL_CTL_PWM)
level = level * PWM_MAX / BL_MAX_LEVEL ;
WRITE_CBUS_REG_BITS(PWM_PWM_D, (PWM_MAX - level), 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_D, level, 16, 16); //pwm high
#endif
}
static void set_hpll_hdmi_od(unsigned div)
{
switch(div){
case 1:
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 0, 18, 2);
break;
case 2:
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 1, 18, 2);
break;
case 3:
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 1, 16, 2);
break;
case 4:
WRITE_CBUS_REG_BITS(HHI_VID_PLL_CNTL, 3, 18, 2);
break;
default:
break;
}
}
void set_backlight_level(unsigned level)
{
level = level>BL_MAX_LEVEL ? BL_MAX_LEVEL:(level<BL_MIN_LEVEL ? BL_MIN_LEVEL:level);
printk("\n\nlcd parameter: set backlight level: %d.\n\n", level);
#if (BL_CTL==BL_CTL_GPIO)
WRITE_MPEG_REG(PERIPHS_PIN_MUX_2, READ_MPEG_REG(PERIPHS_PIN_MUX_2)|(1 << 3)); //GPIOD_1 enable PWM_D for LCD_BL_PWM
WRITE_MPEG_REG(PERIPHS_PIN_MUX_1, READ_MPEG_REG(PERIPHS_PIN_MUX_1)&~(1 << 28)); //GPIOD_1 disable LCD_VGHL_PWM
SET_CBUS_REG_MASK(PWM_MISC_REG_CD, (1 << 1)|(1 << 23)); //Enable PWM_D clock,Enable PWM_D output,select XTAL
level = level * PWM_MAX / BL_MAX_LEVEL ;
WRITE_MPEG_REG(PWM_PWM_D, (level << 16) | ((PWM_MAX - level) << 0));
#elif (BL_CTL==BL_CTL_PWM)
level = level * PWM_MAX / BL_MAX_LEVEL ;
WRITE_CBUS_REG_BITS(PWM_PWM_C, (PWM_MAX - level), 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_C, level, 16, 16); //pwm high
#endif
}
static void aml_8726m_set_bl_level(unsigned level)
{
unsigned cs_level, hi, low;
#if 1
if (level <= 0)
{
cs_level = 0;
}
else if (level > 0 && level < 255)
{
cs_level = level * 235;
}
else
cs_level = BL_MAX_LEVEL;
low = cs_level;
hi = BL_MAX_LEVEL - low;
//WRITE_CBUS_REG_BITS(VGHL_PWM_REG0, cs_level, 0, 4);
WRITE_CBUS_REG_BITS(PWM_PWM_A,(low/50),0,16); //low
WRITE_CBUS_REG_BITS(PWM_PWM_A,(hi/50),16,16); //hi
#else
if (level <= 30)
{
cs_level = 11640;
}
else if (level > 30 && level < 218)
{
cs_level = (level - 31) * 260 + 11640;
}
else
cs_level = BL_MAX_LEVEL;
low = cs_level;
hi = BL_MAX_LEVEL - low;
//WRITE_CBUS_REG_BITS(VGHL_PWM_REG0, cs_level, 0, 4);
WRITE_CBUS_REG_BITS(PWM_PWM_A,low,0,16); //low
WRITE_CBUS_REG_BITS(PWM_PWM_A,hi,16,16); //hi
#endif
}
void power_on_backlight(void)
{
lvds_port_enable();
//BL_EN: GPIOD_1(PWM_D)
WRITE_CBUS_REG_BITS(LED_PWM_REG0, 1, 12, 2);
msleep(300);
#if (BL_CTL==BL_CTL_GPIO)
WRITE_MPEG_REG(0x2013, READ_MPEG_REG(0x2013) | (1 << 17));
WRITE_MPEG_REG(0x2012, READ_MPEG_REG(0x2012) & ~(1 << 17));
#elif (BL_CTL==BL_CTL_PWM)
int pwm_div=0; //pwm_freq=24M/(pwm_div+1)/PWM_MAX
WRITE_CBUS_REG_BITS(PWM_PWM_D, 0, 0, 16); //pwm low
WRITE_CBUS_REG_BITS(PWM_PWM_D, PWM_MAX, 16, 16); //pwm high
SET_CBUS_REG_MASK(PWM_MISC_REG_CD, ((1 << 23) | (pwm_div<<16) | (1<<1))); //enable pwm clk & pwm output
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_2, (1<<3)); //enable pwm pinmux
#endif
//printk("\n\nLCD: power_on_backlight.\n\n");
}
void lowlevel_init(void* cur,void * target)
{
#if 0
if(cur != target) //r0!=r1
{
//running from spi
// take me as a spi rom boot mode
romboot_info->por_cfg = POR_INTL_SPI |
(READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK));
romboot_info->boot_id = 0;//boot from spi
/// Release pull up registers .
}
#endif
power_hold();
backlight_off();
//changed by Elvis, add uart rx pull up
//pull up LINUX_RX(B15--->GPIOE_19) reg (7422y v1.pdf)
//GPIOE_19(M1-Apps v25- 2010-07-19-BGA372_297-6.xls serach B15)
WRITE_CBUS_REG( PAD_PULL_UP_REG3, READ_CBUS_REG(PAD_PULL_UP_REG3) & ~(1<<2) ); // Meson-pull-up-down_table.xlsx ( GPIOE_19 is PAD_PULL_UP_REG3---0x203e 2bits)
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
memory_pll_init(0,NULL);
serial_puts("\nFirmware start at: ");
serial_put_dword(get_timer(0));
#if CONFIG_ENABLE_SPL_DEBUG_ROM
__udelay(100000);//wait for a uart input
if(serial_tstc())
{
debug_rom(__FILE__,__LINE__);
}
#else
__udelay(1000);//delay 1 ms , wait pll ready
#endif
// writel((0<<22)|1000000,P_WATCHDOG_TC);//enable Watchdog
unsigned por_cfg;
#if CONFIG_ENABLE_SPL_DEBUG_ROM
if(ddr_init_test())
debug_rom(__FILE__,__LINE__);
#else
do{
}while(ddr_init_test());
#endif
serial_puts("\nFirmware started, now starting u-boot...");
}
void lowlevel_init(void* cur,void * target)
{
int i;
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
serial_init((__plls.uart&(~0xfff))|(CONFIG_CRYSTAL_MHZ*1000000/(115200*4)));
// serial_init_firmware(__plls.uart);
}
static int meson_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
meson_mask_irq(INT_TIMER_C);
/* use a big number to clear previous trigger cleanly */
SET_CBUS_REG_MASK(ISA_TIMERC, evt & 0xffff);
meson_ack_irq(INT_TIMER_C);
/* then set next event */
WRITE_CBUS_REG_BITS(ISA_TIMERC, evt, 0, 16);
meson_unmask_irq(INT_TIMER_C);
return 0;
}
static void __efuse_write_byte( unsigned long addr, unsigned long data )
{
unsigned long auto_wr_is_enabled = 0;
if ( READ_CBUS_REG( EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_ENABLE_BIT ) )
{
auto_wr_is_enabled = 1;
}
else
{
/* temporarily enable Write mode */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_ON,
CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
}
/* write the address */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, addr,
CNTL1_BYTE_ADDR_BIT, CNTL1_BYTE_ADDR_SIZE );
/* set starting byte address */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_ON,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_OFF,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
/* write the byte */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, data,
CNTL1_BYTE_WR_DATA_BIT, CNTL1_BYTE_WR_DATA_SIZE );
/* start the write process */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_ON,
CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_OFF,
CNTL1_AUTO_WR_START_BIT, CNTL1_AUTO_WR_START_SIZE );
/* dummy read */
READ_CBUS_REG( EFUSE_CNTL1 );
while ( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_WR_BUSY_BIT ) )
{
udelay(1);
}
/* if auto write wasn't enabled and we enabled it, then disable it upon exit */
if (auto_wr_is_enabled == 0 )
{
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_ENABLE_OFF,
CNTL1_AUTO_WR_ENABLE_BIT, CNTL1_AUTO_WR_ENABLE_SIZE );
}
}
void freezing_main(void)
{
int i;
//writel((1<<22)|100000,P_WATCHDOG_TC);//enable Watchdog 1 seconds
//Adjust 1us timer base
WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5);
/*
Select TimerE 1 us base
*/
clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8);
cooling();
chip_reset();
}
static void __efuse_read_dword( unsigned long addr, unsigned long *data )
{
unsigned long auto_rd_is_enabled = 0;
if( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_RD_ENABLE_BIT ) )
{
auto_rd_is_enabled = 1;
}
else
{
/* temporarily enable Read mode */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_RD_ENABLE_ON,
CNTL1_AUTO_RD_ENABLE_BIT, CNTL1_AUTO_RD_ENABLE_SIZE );
}
/* write the address */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, addr,
CNTL1_BYTE_ADDR_BIT, CNTL1_BYTE_ADDR_SIZE );
/* set starting byte address */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_ON,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_BYTE_ADDR_SET_OFF,
CNTL1_BYTE_ADDR_SET_BIT, CNTL1_BYTE_ADDR_SET_SIZE );
/* start the read process */
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_ON,
CNTL1_AUTO_RD_START_BIT, CNTL1_AUTO_RD_START_SIZE );
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_WR_START_OFF,
CNTL1_AUTO_RD_START_BIT, CNTL1_AUTO_RD_START_SIZE );
/* dummy read */
READ_CBUS_REG( EFUSE_CNTL1 );
while ( READ_CBUS_REG(EFUSE_CNTL1) & ( 1 << CNTL1_AUTO_RD_BUSY_BIT ) )
{
udelay(1);
}
/* read the 32-bits value */
( *data ) = READ_CBUS_REG( EFUSE_CNTL2 );
/* if auto read wasn't enabled and we enabled it, then disable it upon exit */
if ( auto_rd_is_enabled == 0 )
{
WRITE_CBUS_REG_BITS( EFUSE_CNTL1, CNTL1_AUTO_RD_ENABLE_OFF,
CNTL1_AUTO_RD_ENABLE_BIT, CNTL1_AUTO_RD_ENABLE_SIZE );
}
//printk(KERN_INFO "__efuse_read_dword: addr=%ld, data=0x%lx\n", addr, *data);
}