void set_mpeg_clock(int clock)
{
clock_t *p = find_pll(clock);
if (!p) {
return;
}
Wr(HHI_OTHER_PLL_CNTL, p->setting); // other PLL set to 175Mhz
Wr(HHI_MPEG_CLK_CNTL, // MPEG clk81 set to other/2
(0 << 12) | // select other PLL
(1 << 0) | // div2
(1 << 7) | // cntl_hi_mpeg_div_en, enable gating
(1 << 8); // Connect clk81 to the PLL divider output
Wr(HHI_MALI_CLK_CNTL, // GPU clock set to other/2
(1 << 9) | // select "other" PLL
(1 << 8) | // Enable gated clock
(1 << 0)); // Divide the "other" PLL output by 2
Wr(HHI_HDMI_CLK_CNTL, // HDMI clock set to other/4
(1 << 9) | // select "other" PLL
(1 << 8) | // Enable gated clock
(3 << 0)); // Divide the "other" PLL output by 4
}
void u_boot_init_lvds()
{
int j;
int m = 10, n = 34;
unsigned long reverse = simple_strtoul(getenv ("port_reverse"), NULL, 16);
if(reverse == 1) {
port_reverse = 1;
}
//GPIOX_54 LVDS power off
set_gpio_val(GPIOX_bank_bit32_63(54), GPIOX_bit_bit32_63(54), 0);
set_gpio_mode(GPIOX_bank_bit32_63(54), GPIOX_bit_bit32_63(54), 0);
//GPIOX_54 LVDS power on
set_gpio_val(GPIOX_bank_bit32_63(54), GPIOX_bit_bit32_63(54), 1);
set_gpio_mode(GPIOX_bank_bit32_63(54), GPIOX_bit_bit32_63(54), 0);
for (j=0; j<n; j++)
udelay(1000);
Wr(REG_LVDS_PHY_CNTL4, Rd(REG_LVDS_PHY_CNTL4)|0xfff); //LVDS_MDR_PU
Wr(REG_LVDS_PHY_CNTL5, Rd(REG_LVDS_PHY_CNTL5)|(0xf<<11)); //LVDS_REFCTL<4:0>=<01111>
Wr(REG_LVDS_PHY_CNTL0,0xfff); //LVDS_PDN_A*=1, LVDS_PDN_B*=1
/*for (j=0; j<m; j++)
udelay(1000);*/
//GPIOB_6 Backlight power on
set_gpio_val(GPIOB_bank_bit0_7(6), GPIOB_bank_bit0_7(6), 0);
set_gpio_mode(GPIOB_bank_bit0_7(6), GPIOB_bank_bit0_7(6), 0);
lvds_set_current_vmode(VMODE_LVDS_1080P);
}
static int lvds_suspend(void)
{
int j;
long m = 250, n= 200;
if (pdata->lvds_backlight_power_off)
pdata->lvds_backlight_power_off();
for (j=0; j<n; j++)
udelay(1000);
Wr(REG_LVDS_PHY_CNTL4, Rd(REG_LVDS_PHY_CNTL4)&(~0xfff));//LVDS_MDR_PU
Wr(REG_LVDS_PHY_CNTL5, Rd(REG_LVDS_PHY_CNTL5)&(~(0xc<<11))); //LVDS_REFCTL<3:2> = 0
Wr(REG_LVDS_PHY_CNTL0,0); //LVDS_PDN_A*=0, LVDS_PDN_B*=0
lvds_init_flag = 0;
for (j=0; j<m; j++)
udelay(1000);
if (pdata->lvds_panel_power_off)
pdata->lvds_panel_power_off();
printk("vout lvds suspend\n");
return 0;
}
static int lvds_set_current_vmode(vmode_t mode)
{
int i, j, count = ARRAY_SIZE(lvds_info);
long m = 10, n = 10;
for(i=0; i<count; i++) {
if(lvds_info[i].mode==mode) {
cur_lvds_index = i;
break;
}
}
if(i == count)
return -EINVAL;
/* to do */
if (lvds_init_flag == 0) {
/*for (j=0; j<m; j++)
udelay(1000);*/
clk_util_set_video_clock( 0x00000641, 1 ); // divide by 1
init_lvds_phy();
init_lvds();
Wr(ENCP_VIDEO_EN, 1);
Wr(VPP_HOLD_LINES, 0x08080808);
lvds_enable_vsync_interrupt();
WRITE_MPEG_REG(VPP_POSTBLEND_H_SIZE, lvds_info[0].width);
/*for (j=0; j<n; j++)
udelay(1000);*/
lvds_init_flag = 1;
}
return 0;
}
vector<uchar> CalculateMidstate(vector<uchar> workdata)
{
uint hash[8];
uint initial[8];
uint work[64];
memcpy(hash, sha256_init, 8*sizeof(uint));
memcpy(work, &workdata[0], 16*sizeof(uint));
memcpy(initial, hash, 8*sizeof(uint));
for(uint i=0; i<64; ++i)
{
if (i>=16)
work[i] = work[i-7] + work[i-16] + Wr(work[i-2],17,19,10) + Wr(work[i-15],7,18,3);
sharound(hash[(0-i)&7],hash[(1-i)&7],hash[(2-i)&7],hash[(3-i)&7],hash[(4-i)&7],hash[(5-i)&7],hash[(6-i)&7],hash[(7-i)&7],work[i],K[i]);
}
for(uint i=0; i<8; ++i)
hash[i] += initial[i];
vector<uchar> ret;
ret.assign(32,0);
for(uint i=0; i<32; ++i)
{
ret[i] = ((uchar*)hash)[i];
}
return ret;
}
void srcif_hybrid_fsm_goto_rst_all()
{
int data32 = 0;
LOGD(TAG_VPP, "hybrid fsm reset all\n");
Wr(SRCIF_WRAP_CTRL1 , (Rd(SRCIF_WRAP_CTRL1) | 0x10));
Wr(SRCIF_WRAP_CTRL1 , (Rd(SRCIF_WRAP_CTRL1) & 0xffffffef));
}
// -----------------------------------------------------------------
// clk_util_set_video_clock()
//
// This function sets the "master clock" in the video clock
// module $clk_rst_tst/rtl/crt_video
//
// wire cntl_sclk_n = hi_video_clk_cntl[10];
// wire [1:0] cntl_vclk3_mux = hi_video_clk_cntl[9:8];
// wire [1:0] cntl_vclk2_mux = hi_video_clk_cntl[7:6];
// wire [1:0] cntl_vclk1_mux = hi_video_clk_cntl[5:4];
// wire [3:0] cntl_xd = hi_video_clk_cntl[3:0];
static void clk_util_set_video_clock( unsigned long hiu_reg, unsigned long xd )
{
// switch video clock to sclk_n and enable the PLL
Wr( HHI_VID_CLK_CNTL, Rd(HHI_VID_CLK_CNTL) & ~(1 << 10) ); // Switch to the SCLK
// delay 2uS to allow the sync mux to switch over
Wr( ISA_TIMERE, 0);
while( Rd(ISA_TIMERE) < 2 ) {}
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_VID_PLL_CNTL, (0 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
Wr( HHI_VID_PLL_CNTL, hiu_reg );
// Setup external divider in $clk_rst_tst/rtl/crt_video.v
// wire [3:0] cntl_div_by_1 = hi_vid_clk_cntl[3:0]; // for LVDS we can divide by 1 (pll direct)
// wire cntl_vclk_gate = hi_vid_clk_cntl[0]; // needed to mux divide by 1
//
// wire [7:0] cntl_xd = hi_vid_clk_div[7:0];
if( xd == 1 ) {
// Set divide by 1 in crt_video
Wr( HHI_VID_CLK_CNTL, Rd(HHI_VID_CLK_CNTL) | (0xF << 0) );
} else {
Wr( HHI_VID_CLK_CNTL, (Rd(HHI_VID_CLK_CNTL) & ~(0xF << 0)) ); // disable divide by 1 control
}
Wr( HHI_VID_CLK_DIV, (Rd(HHI_VID_CLK_DIV) & ~(0xFF << 0)) | (xd-1) ); // setup the XD divider value
// delay 5uS
Wr( ISA_TIMERE, 0);
while( Rd(ISA_TIMERE) < 5 ) {}
Wr( HHI_VID_CLK_CNTL, Rd(HHI_VID_CLK_CNTL) | (1 << 10) ); // Switch to the PLL
// delay 2uS
Wr( ISA_TIMERE, 0);
while( Rd(ISA_TIMERE) < 2 ) {}
}
int check_burning_wind(int** forest, int row_index, int col_index, int neighbourhood_type, int wind_speed, int wind_direction, long double pImmune,int rows, int cols)
{
int i=row_index;
int j=col_index;
int neighbour_status = -5;
switch(wind_speed)
{
case 0:
return TREE;
break;
case 2:
switch(wind_direction)
{
case SOUTH:
neighbour_status = forest[Nr(Nr(i))%rows][Nc(Nc(j))%cols];
break;
case NORTH:
neighbour_status = forest[Sr(Sr(i))%rows][Sc(Sc(j))%cols];
break;
case EAST:
neighbour_status = forest[Wr(Wr(i))%rows][Wc(Wc(j))%cols];
break;
case WEST:
neighbour_status = forest[Er(Er(i))%rows][Ec(Ec(j))%cols];
break;
}
if (pImmune<U && neighbour_status == BURNING)
return BURNING;
case 1:
neighbour_status = -5;
switch(wind_direction)
{
case SOUTH:
neighbour_status = forest[Nr(i)][Nc(j)];
break;
case NORTH:
neighbour_status = forest[Sr(i)][Sc(j)];
break;
case EAST:
neighbour_status = forest[Wr(i)][Wc(j)];
break;
case WEST:
neighbour_status = forest[Er(i)][Ec(j)];
break;
}
if (pImmune<U && neighbour_status == BURNING)
return BURNING;
else
return TREE;
}
}
void srcif_hybrid_fsm_init()
{
int data32 = 0;
Wr(SRCIF_WRAP_CTRL , 0x80000024);
Wr(SRCIF_WRAP_CTRL1, 0x03100003);
Wr(SRCIF_WRAP_CTRL1, 0xc3100003);
Wr(SRCIF_WRAP_CNT0 , 0x00000010);
Wr(SRCIF_WRAP_CNT1 , 0x00000020);
Wr(SRCIF_WRAP_CNT2 , 0x00000030);
Wr(SRCIF_WRAP_CNT3 , 0x00000020);
Wr(SRCIF_WRAP_CNT5 , 0x00000010);
Wr(SRCIF_WRAP_CNT6 , 0x00000020);
Wr(SRCIF_WRAP_CTRL , 0x80200024);
}
void srcif_fsm_init()
{
int data32 = 0;
Wr(SRCIF_WRAP_CTRL , 0x00000024);
Wr(SRCIF_WRAP_CTRL1, 0x00340000);
Wr(SRCIF_WRAP_CTRL1, 0xc0340000);
Wr(SRCIF_WRAP_CNT0 , 0x00000010);
Wr(SRCIF_WRAP_CNT1 , 0x00000020);
Wr(SRCIF_WRAP_CNT2 , 0x00000030);
Wr(SRCIF_WRAP_CNT3 , 0x00000040);
Wr(SRCIF_WRAP_CNT5 , 0x00000050);
Wr(SRCIF_WRAP_CNT6 , 0x00000060);
//Wr(SRCIF_WRAP_CTRL , 0x03200020);
Wr(SRCIF_WRAP_CTRL , 0x00000024);
}
int do_neighbours_burn(int** forest,int row_index,int col_index)
{
return (forest[Nr(row_index)][Nc(col_index)]==BURNING ||
forest[Er(row_index)][Ec(col_index)]==BURNING ||
forest[Wr(row_index)][Wc(col_index)]==BURNING ||
forest[Sr(row_index)][Sc(col_index)]==BURNING
);
}
int VSYNCOSD_WR_MPEG_REG(unsigned long addr, unsigned long val)
{
if(rdma_enable)
{
update_table_item(addr,val);
}else{
Wr(addr,val);
}
return 0;
}
void srcif_hybrid_fsm_ctrl()
{
int data32 = 0;
//check status register
data32 = Rd(SRCIF_WRAP_STATUS);
LOGD(TAG_VPP, "status = %x\n",data32);
LOGD(TAG_VPP, "state = %x\n",data32 & 0x7);
if ((data32 & 0x7) == 0x0) {
LOGD(TAG_VPP, "state: st_idle\n");
}
else if ((data32 & 0x7) == 0x1) {
delay_us(100);
LOGD(TAG_VPP, "state: st_rst_all, goto st_clk_mux\n");
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffffdf);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) | 0x20);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffffdf);
}
else if ((data32 & 0x7) == 0x2) {
LOGD(TAG_VPP, "state: st_mux_clk\n");
data32 = Rd(SRCIF_WRAP_STATUS);
while ((data32 & 0x400) != 0x400) {
delay_us(1);
data32 = Rd(SRCIF_WRAP_STATUS);
}
if ((data32 & 0x0800) == 0x0800) {
LOGD(TAG_VPP, "state: st_mux_clk, stbl , goto st_hdmi\n");
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffff7f);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) | 0x80);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffff7f);
}
else {
LOGD(TAG_VPP, "state: st_clk_mux, un stbl , goto st_ptn\n");
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffffbf);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) | 0x40);
Wr(SRCIF_WRAP_CTRL1,Rd(SRCIF_WRAP_CTRL1) & 0xffffffbf);
}
}
else if ((data32 & 0x7) == 0x3) {
LOGD(TAG_VPP, "state: st_hdmi\n");
}
else if ((data32 & 0x7) == 0x4) {
LOGD(TAG_VPP, "state: st_ptn\n");
}
}
void srcif_pure_sw_ptn()
{
static int do_ptn_flag = 1;
if(do_ptn_flag == 0){
srcif_pure_ptn_flag = 1;
return;
}
if(do_ptn_flag){
int data32 = 0;
Wr(SRCIF_WRAP_CTRL , 0x00000020);
//step 1, rst fifo, vmux, gate vpu, force fifo_en, vmux_en, vmux_sel
Wr(SRCIF_WRAP_CTRL , 0x0802aaa0);
delay_us(1);
//step 2, clock mux to ptn
Wr(SRCIF_WRAP_CTRL , 0x0812aaa0);
delay_us(1);
//step 3, Need a wait pll lock here
//step 4, release rst of vmux, en vpu_clk_en
Wr(SRCIF_WRAP_CTRL , 0x0c12aba0);
delay_us(1);
//step 5, enable ptn_en, vmux_en
Wr(SRCIF_WRAP_CTRL , 0x0c12bbe0);
Wr(VP_CTRL , Rd(VP_CTRL) | 0x2);
delay_us(1);
}
do_ptn_flag = 0;
}
/* This returns 1 if any neighbours burn, 0 otherwise */
int do_neighbours_burn(int** forest, int row_index, int col_index, int neighbourhood_type){
int i=row_index;
int j=col_index;
switch(neighbourhood_type){
case VON_NEUMANN:
return ((forest[Nr(i)][Nc(j)]>=BURNING &&
forest[Nr(i)][Nc(j)]<=OLD_BURNING) ||
(forest[Er(i)][Ec(j)]>=BURNING &&
forest[Er(i)][Ec(j)]<=OLD_BURNING) ||
(forest[Wr(i)][Wc(j)]>=BURNING &&
forest[Wr(i)][Wc(j)]<=OLD_BURNING) ||
(forest[Sr(i)][Sc(j)]>=BURNING &&
forest[Sr(i)][Sc(j)]<=OLD_BURNING)
);
case MOORE:
return ((forest[Nr(i)][Nc(j)]>=BURNING &&
forest[Nr(i)][Nc(j)]<=OLD_BURNING) ||
(forest[Er(i)][Ec(j)]>=BURNING &&
forest[Er(i)][Ec(j)]<=OLD_BURNING) ||
(forest[Wr(i)][Wc(j)]>=BURNING &&
forest[Wr(i)][Wc(j)]<=OLD_BURNING) ||
(forest[Sr(i)][Sc(j)]>=BURNING &&
forest[Sr(i)][Sc(j)]<=OLD_BURNING)
||
//Diagonals
(forest[NEr(i)][NEc(j)]>=BURNING &&
forest[NEr(i)][NEc(j)]<=OLD_BURNING) ||
(forest[SEr(i)][SEc(j)]>=BURNING &&
forest[SEr(i)][SEc(j)]<=OLD_BURNING) ||
(forest[NWr(i)][NWc(j)]>=BURNING &&
forest[NWr(i)][NWc(j)]<=OLD_BURNING) ||
(forest[SWr(i)][SWc(j)]>=BURNING &&
forest[SWr(i)][SWc(j)]<=OLD_BURNING)
);
default:
return 0;
}
}
/* This counts the number of burning neighbours */
int count_burning_neighbours(int** forest, int row_index, int col_index, int neighbourhood_type){
int neighbors_on_fire=0;
int i=row_index;
int j=col_index;
switch(neighbourhood_type){
case VON_NEUMANN:
if(forest[Nr(i)][Nc(j)]>=BURNING && forest[Nr(i)][Nc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Er(i)][Ec(j)]>=BURNING && forest[Er(i)][Ec(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Wr(i)][Wc(j)]>=BURNING && forest[Wr(i)][Wc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Sr(i)][Sc(j)]>=BURNING && forest[Sr(i)][Sc(j)]<=OLD_BURNING)
neighbors_on_fire++;
break;
case MOORE:
if(forest[Nr(i)][Nc(j)]>=BURNING && forest[Nr(i)][Nc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Er(i)][Ec(j)]>=BURNING && forest[Er(i)][Ec(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Wr(i)][Wc(j)]>=BURNING && forest[Wr(i)][Wc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[Sr(i)][Sc(j)]>=BURNING && forest[Sr(i)][Sc(j)]<=OLD_BURNING)
neighbors_on_fire++;
/* Diagonals */
if(forest[NEr(i)][NEc(j)]>=BURNING && forest[NEr(i)][NEc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[SEr(i)][SEc(j)]>=BURNING && forest[SEr(i)][SEc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[NWr(i)][NWc(j)]>=BURNING && forest[NWr(i)][NWc(j)]<=OLD_BURNING)
neighbors_on_fire++;
if(forest[SWr(i)][SWc(j)]>=BURNING && forest[SWr(i)][SWc(j)]<=OLD_BURNING)
neighbors_on_fire++;
break;
default:
break;
}
return neighbors_on_fire;
}
// -----------------------------------------
// clk_util_lvds_set_clk_div()
// -----------------------------------------
// This task is used to setup the LVDS dividers.
//
// Dual Pixel Mode
// clk_util_lvds_set_clk_div( 2, // unsigned long divn_sel, // select divide by 3.5
// 7, // unsigned long divn_tcnt, // ignored
// 0 ); // unsigned long div2_en, // divide by 1 for LVDS
//
// Single Pixel Mode
// clk_util_lvds_set_clk_div( 1, // unsigned long divn_sel, // select divide by N
// 7, // unsigned long divn_tcnt, // divide by 7
// 0 ); // unsigned long div2_en, // divide by 1 for LVDS
static void clk_util_lvds_set_clk_div( unsigned long divn_sel,
unsigned long divn_tcnt,
unsigned long div2_en )
{
// assign lvds_div_phy_clk_en = tst_lvds_tmode ? 1'b1 : phy_clk_cntl[10];
// assign lvds_div_div2_sel = tst_lvds_tmode ? atest_i[5] : phy_clk_cntl[9];
// assign lvds_div_sel = tst_lvds_tmode ? atest_i[7:6] : phy_clk_cntl[8:7];
// assign lvds_div_tcnt = tst_lvds_tmode ? 3'd6 : phy_clk_cntl[6:4];
// If dividing by 1, just select the divide by 1 path
if( divn_tcnt == 1 ) {
divn_sel = 0;
}
Wr( REG_LVDS_PHY_CLK_CNTL, ((Rd(REG_LVDS_PHY_CLK_CNTL) & ~((0x3 << 7) | (1 << 9) | (0x7 << 4))) | ((1 << 10) | (divn_sel << 7) | (div2_en << 9) | (((divn_tcnt-1)&0x7) << 4))) );
}
static int lvds_resume(void)
{
int j;
int m = 200, n = 300;
if (pdata->lvds_panel_power_on)
pdata->lvds_panel_power_on();
for (j=0; j<n; j++)
udelay(1000);
Wr(REG_LVDS_PHY_CNTL4, Rd(REG_LVDS_PHY_CNTL4)|0xfff); //LVDS_MDR_PU
Wr(REG_LVDS_PHY_CNTL5, Rd(REG_LVDS_PHY_CNTL5)|(0xf<<11)); //LVDS_REFCTL<4:0>=<01111>
Wr(REG_LVDS_PHY_CNTL0,0xfff); //LVDS_PDN_A*=1, LVDS_PDN_B*=1
for (j=0; j<m; j++)
udelay(1000);
if (pdata->lvds_backlight_power_on)
pdata->lvds_backlight_power_on();
printk("vout lvds resume\n");
return 0;
}
void set_system_clock(int clock)
{
clock_t *p = find_pll(clock);
if (!p) {
return;
}
Wr(HHI_SYS_PLL_CNTL, p->setting); // system PLL set to 900Mhz
Wr(HHI_A9_CLK_CNTL, // A9 clk set to system clock/2
(0 << 10) | // 0 - sys_pll_clk, 1 - audio_pll_clk
(0 << 0) | // 0 - sys/audio pll clk, 1 - XTAL
(1 << 2) | // div2
(1 << 7); // Connect A9 to the PLL divider output
}
void init_lvds_phy(void)
{
unsigned tmp_add_data;
Wr(REG_LVDS_PHY_CNTL4, Rd(REG_LVDS_PHY_CNTL4)|0xfff);
Wr(REG_LVDS_PHY_CNTL3, 0x3f);
tmp_add_data = 0;
tmp_add_data |= 0xf<<0; //LVDS_PREM_CTL<3:0>=<1111>
tmp_add_data |= 0x3 << 4; //LVDS_SWING_CTL<3:0>=<0011>
tmp_add_data |= 0x2<<8 ; //LVDS_VCM_CTL<2:0>=<010>
tmp_add_data |= 0xf<<11; //LVDS_REFCTL<4:0>=<01111>
Wr(REG_LVDS_PHY_CNTL5, tmp_add_data);
Wr(REG_LVDS_PHY_CNTL0,0xfff);
Wr(REG_LVDS_PHY_CNTL1,0xfff);
Wr(REG_LVDS_PHY_CNTL2,0xfff);
Wr(REG_LVDS_PHY_CNTL6,0xcccc);
Wr(REG_LVDS_PHY_CNTL7,0xcccc);
Wr(REG_LVDS_PHY_CNTL8,0xcccc);
}
//Initial D2D3 Register
void d2d3_set_def_config(d2d3_param_t *parm)
{
unsigned short i = 0;
parm->input_w = 0;
parm->input_h = 0;
parm->output_w = 0;
parm->output_h = 0;
parm->dpg_path = D2D3_DPG_MUX_VPP;
parm->dbr_path = D2D3_DBR_MUX_VPP;
parm->dbr_mode = LINE_INTERLEAVED;
//enable clk_d2d3_reg
Wr_reg_bits(D2D3_INTF_CTRL0,1,ON_CLK_D2D3_REG_BIT,ON_CLK_D2D3_REG_WID); //d2d3_intf_ctrl0[23:22];
//load default config as 1080p
for(i=0; i<D2D3_REG_NUM; i++){
Wr(D2D3_CBUS_BASE + i, d2d3_reg_table[i]);
}
return;
}
void set_ddr_clock(struct ddr_set * timing_reg)
{
/*
#ifdef ENABLE_POWER_SAVING
APB_Wr(PCTL_DLLCR_ADDR, APB_Rd(PCTL_DLLCR_ADDR)|(7<<2));
#endif
*/
M6_PLL_RESET(HHI_DDR_PLL_CNTL);
Wr(HHI_DDR_PLL_CNTL2,M6_DDR_PLL_CNTL_2);
Wr(HHI_DDR_PLL_CNTL3,M6_DDR_PLL_CNTL_3);
Wr(HHI_DDR_PLL_CNTL4,M6_DDR_PLL_CNTL_4);
#ifdef CONFIG_CMD_DDR_TEST
if((Rd(PREG_STICKY_REG0) & 0xffff) == 0x2012){
zqcr = (Rd(PREG_STICKY_REG0) >> 16);
Wr(HHI_DDR_PLL_CNTL, Rd(PREG_STICKY_REG1));
Wr(PREG_STICKY_REG0, 0);
Wr(PREG_STICKY_REG1, 0);
}
void srcif_fsm_no_mute_stbl()
{
Wr(SRCIF_WRAP_CTRL1, (Rd(SRCIF_WRAP_CTRL1) & 0xffbfffff));
}
SHARETEST_VALUE ShareTest_BTC(uint* workdata, uint* target)
{
uint hash[8];
uint initial[8];
uint work[64];
memcpy(hash, sha256_init, 8*sizeof(uint));
memcpy(work, workdata, 16*sizeof(uint));
memcpy(initial, hash, 8*sizeof(uint));
for(uint i=0; i<64; ++i)
{
if (i>=16)
work[i] = work[i-7] + work[i-16] + Wr(work[i-2],17,19,10) + Wr(work[i-15],7,18,3);
sharound(hash[(0-i)&7],hash[(1-i)&7],hash[(2-i)&7],hash[(3-i)&7],hash[(4-i)&7],hash[(5-i)&7],hash[(6-i)&7],hash[(7-i)&7],work[i],K[i]);
}
for(uint i=0; i<8; ++i)
hash[i] += initial[i];
memset(work, 0, 16*sizeof(uint));
memcpy(work, workdata+16, 4*sizeof(uint));
work[4] = (1U<<31U);
work[15] = 0x280;
memcpy(initial, hash, 8*sizeof(uint));
for(uint i=0; i<64; ++i)
{
if (i>=16)
work[i] = work[i-7] + work[i-16] + Wr(work[i-2],17,19,10) + Wr(work[i-15],7,18,3);
sharound(hash[(0-i)&7],hash[(1-i)&7],hash[(2-i)&7],hash[(3-i)&7],hash[(4-i)&7],hash[(5-i)&7],hash[(6-i)&7],hash[(7-i)&7],work[i],K[i]);
}
for(uint i=0; i<8; ++i)
hash[i] += initial[i];
memset(work, 0, 16*sizeof(uint));
memcpy(work, hash, 8*sizeof(uint));
work[8] = (1U<<31U);
work[15] = 0x100;
memcpy(hash, sha256_init, 8*sizeof(uint));
memcpy(initial, hash, 8*sizeof(uint));
for(uint i=0; i<64; ++i)
{
if (i>=16)
work[i] = work[i-7] + work[i-16] + Wr(work[i-2],17,19,10) + Wr(work[i-15],7,18,3);
sharound(hash[(0-i)&7],hash[(1-i)&7],hash[(2-i)&7],hash[(3-i)&7],hash[(4-i)&7],hash[(5-i)&7],hash[(6-i)&7],hash[(7-i)&7],work[i],K[i]);
}
for(uint i=0; i<8; ++i)
hash[i] = EndianSwap(hash[i]+initial[i]);
if (hash[7] != 0)
return ST_HNOTZERO;
for(int i=6; i>=0; --i)
{
if (hash[i] > target[i])
{
//cout << "Hash > target! :(" << endl;
return ST_MORETHANTARGET;
}
if (hash[i] < target[i])
{
//cout << "Hash < target! :)" << endl;
return ST_GOOD;
}
}
//cout << "Hash = target! :|" << endl;
return ST_MORETHANTARGET;
/* if (hash[7] == 0)
{
if (globalconfs.log_midhash)
{
fstream filu("hashes.txt", ios_base::out|ios_base::app);
filu << setfill('0');
for(uint i=0; i<8; ++i)
filu << setw(8) << hex << work[i] << " ";
filu << endl;
}
return true;
}
else
{
return false;
}*/
}
void srcif_fsm_clk_freerun()
{
Wr(SRCIF_WRAP_CTRL, (Rd(SRCIF_WRAP_CTRL) | 0x40000));
}
void set_srcif_hdmi2vpu (
int adj_mode ,
int hsize ,
int line_blank_num ,
int reg_rx_drop_tim_ratio , // u6
int reg_lbuf_depth , // u12
int reg_loop0_fifo_lowlmt , // u15
int reg_loop0_fifo_target , // u15
int reg_loop0_fifo_higlmt , // u15
int reg_loop0_error_core0 , // u12
int reg_loop0_error_core1 , // u12
int reg_loop0_error_core_mode , // u1
int reg_loop0_error_lmt , // u14
int reg_loop0_error_gain_lmt , // u8
int reg_loop0_error_gain_raw , // u8
int reg_loop0_error_gain_fin , // u8
int reg_loop0_adj_pad_gain , // u8
int reg_loop0_adj_pad_rs , // u3
int reg_loop0_adj_pad_pxgrouprs , // u3
int reg_verr_stbdet_win0 // u14
)
{
int data32 = 0;
int reg_meas_cyc_mode ; // 1 : keep cycle; 0 : keep time
int reg_rx_loop0_drop_en ;
int reg_tx_loop0_fill_en ;
int reg_rx_drop_num ; // HSYN_NUM+PREDE_NUM;
int reg_rx_drop_line_len ; // HSYN_NUM+PREDE_NUM; // u15
int reg_vblank_hsize_lmt ;
LOGD(TAG_VPP, "=== set_srcif_hdmi_datapath ====\n");
if ( adj_mode==0 ) {
reg_meas_cyc_mode = 1;
reg_rx_loop0_drop_en = 1;
reg_tx_loop0_fill_en = 1;
reg_rx_drop_num = line_blank_num;
reg_rx_drop_line_len = line_blank_num;
}
else if (adj_mode==1) {
reg_meas_cyc_mode = 1;
reg_rx_loop0_drop_en = 0;
reg_tx_loop0_fill_en = 0;
reg_rx_drop_num = line_blank_num;
reg_rx_drop_line_len = line_blank_num;
}
else {
reg_meas_cyc_mode = 0;
reg_rx_loop0_drop_en = 0;
reg_tx_loop0_fill_en = 0;
reg_rx_drop_num = line_blank_num;
reg_rx_drop_line_len = line_blank_num;
}
reg_vblank_hsize_lmt = hsize;
// set control reg
Wr_reg_bits(VPU_SRCIF_CTRL,reg_meas_cyc_mode,0,1);
data32 = ((reg_rx_loop0_drop_en & 0x1)<<1) |
(reg_tx_loop0_fill_en & 0x1);
Wr_reg_bits(VPU_SRCIF_CTRL,data32,3,2);
Wr_reg_bits(VPU_SRCIF_CTRL,reg_rx_drop_tim_ratio,8,6);
data32 = ((reg_rx_drop_num & 0xffff)<<16) |
(reg_rx_drop_line_len & 0xffff);
Wr(VPU_SRCIF_RX_DROP_NUM, data32);
data32 = ((reg_vblank_hsize_lmt & 0xffff)<<16) |
(reg_lbuf_depth & 0xfff );
Wr(VPU_SRCIF_LBUF_DEPTH, data32);
data32 = ((reg_loop0_fifo_lowlmt & 0x7fff)<<16) |
(reg_loop0_fifo_higlmt & 0x7fff);
Wr(VPU_SRCIF_LOOP_FIFO_LMT, data32);
data32 = ((reg_loop0_fifo_target & 0x7fff)<<16) |
(reg_loop0_error_lmt & 0x3fff);
Wr(VPU_SRCIF_LOOP_FIFO_TARGET, data32);
data32 = ((reg_loop0_error_core_mode & 0x1)<<28) |
((reg_loop0_error_core0 & 0xfff)<<16) |
(reg_loop0_error_core1 & 0xfff);
Wr(VPU_SRCIF_LOOP_ERR_CORE, data32);
data32 = ((reg_loop0_error_gain_lmt & 0xff)<<16) |
((reg_loop0_error_gain_raw & 0xff)<<8 ) |
(reg_loop0_error_gain_fin & 0xff);
Wr(VPU_SRCIF_LOOP_ERR_GAIN, data32);
data32 = ((reg_loop0_adj_pad_rs & 0x7 )<<16) |
((reg_loop0_adj_pad_gain & 0xff)<<8 ) |
((reg_loop0_adj_pad_pxgrouprs & 0x7 )<<4 ) |
(0x2 & 0x3 );
Wr(VPU_SRCIF_LOOP_ADJ_PAD_CFG, data32);
data32 = (reg_verr_stbdet_win0 & 0x3fff);
Wr(VPU_SRCIF_VERR_STBDET_WIN, data32);
}
void srcif_tmg_on(int mode)
{
//mode == 0, 1080p,
//mode == 1, 640x480p
//mode == 2, 4k2k
if (mode == 0) {
Wr(VP_TMGEN_HTOTAL,0x464044b);
Wr(VP_TMGEN_HAVON_H,0x43f0080);
Wr(VP_TMGEN_VAVON_V,0x4570020);
Wr(VP_TMGEN_HSO_H ,0x0050000);
Wr(VP_TMGEN_VSO_H ,0x0050000);
}
else if (mode == 1) {
Wr(VP_TMGEN_HTOTAL,0x20c01af);
Wr(VP_TMGEN_HAVON_H,0x15f0020);
Wr(VP_TMGEN_VAVON_V,0x1ef0010);
Wr(VP_TMGEN_HSO_H ,0x0050000);
Wr(VP_TMGEN_VSO_H ,0x0050000);
Wr(VP_IMG_SIZE,0x1df027f);
}
else if (mode == 2) {
Wr(VP_TMGEN_HTOTAL,0x8c90897);
Wr(VP_TMGEN_HAVON_H,0x79f0020);
Wr(VP_TMGEN_VAVON_V,0x87f0010);
Wr(VP_TMGEN_HSO_H ,0x0050000);
Wr(VP_TMGEN_VSO_H ,0x0050000);
Wr(VP_IMG_SIZE,0x86f0eff);
}
else {
Wr(VP_TMGEN_HTOTAL,0x464044b);
Wr(VP_TMGEN_HAVON_H,0x43f0080);
Wr(VP_TMGEN_VAVON_V,0x4570020);
Wr(VP_TMGEN_HSO_H ,0x0050000);
Wr(VP_TMGEN_VSO_H ,0x0050000);
}
}
void srcif_fsm_fc_unstbl()
{
Wr(SRCIF_WRAP_CTRL , ((Rd(SRCIF_WRAP_CTRL) & 0xff3fffff)| 0x80800000));
}
void srcif_fsm_stbl_from_hdmi()
{
Wr(SRCIF_WRAP_CTRL , (Rd(SRCIF_WRAP_CTRL) && 0xff3fffff));
}
void srcif_fsm_fc_stbl()
{
Wr(SRCIF_WRAP_CTRL , (Rd(SRCIF_WRAP_CTRL) | 0xc00000));
}