ConsolidationStats consolidateTPSki(TermPack& tp) {
auto segments = tp.segments();
ConsolidationStats nil;
if(segments.size()<2) {
nil += WriteIO(segments.back(), 0); //0 since we write all non-consolidants together
return nil;
}
double tokens = tp.convertSeeksToTokens( //exchange seeks for tokens
costIoInMinutes(ReadIO(0,tp.extraSeeks()),
settings.ioMBS, settings.ioSeek, settings.szOfPostingBytes));
std::vector<double> consolidationPriceVector;
auxRebuildCPrice(consolidationPriceVector, segments, settings,tokens);
auto i = int(consolidationPriceVector.size()-1);
while(i>=0 && tokens >= consolidationPriceVector[size_t(i)])
--i;
unsigned offset = i+1;
assert(offset<=segments.size());
if(offset<segments.size()-1) {
auto cons = consolidateSegments(tp.unsafeGetSegments(), offset);
tp.reduceTokens(ConsolidationStats::costInMinutes(cons,
settings.ioMBS, settings.ioSeek, settings.szOfPostingBytes));
return cons;
}
nil += WriteIO(segments.back(),0); //0 since we write all non-consolidants together
return nil;
}
void WsLoadState(int num)
{
FILE* fp;
wchar_t buf[512];
unsigned int value;
int i;
wsprintf(buf, L"%s.%03d", StateName, num);
if ((fp = _wfopen(buf, L"rb")) == NULL)
{
return;
}
MacroLoadNecRegisterFromFile(fp,NEC_IP);
MacroLoadNecRegisterFromFile(fp,NEC_AW);
MacroLoadNecRegisterFromFile(fp,NEC_BW);
MacroLoadNecRegisterFromFile(fp,NEC_CW);
MacroLoadNecRegisterFromFile(fp,NEC_DW);
MacroLoadNecRegisterFromFile(fp,NEC_CS);
MacroLoadNecRegisterFromFile(fp,NEC_DS);
MacroLoadNecRegisterFromFile(fp,NEC_ES);
MacroLoadNecRegisterFromFile(fp,NEC_SS);
MacroLoadNecRegisterFromFile(fp,NEC_IX);
MacroLoadNecRegisterFromFile(fp,NEC_IY);
MacroLoadNecRegisterFromFile(fp,NEC_BP);
MacroLoadNecRegisterFromFile(fp,NEC_SP);
MacroLoadNecRegisterFromFile(fp,NEC_FLAGS);
MacroLoadNecRegisterFromFile(fp,NEC_VECTOR);
MacroLoadNecRegisterFromFile(fp,NEC_PENDING);
MacroLoadNecRegisterFromFile(fp,NEC_NMI_STATE);
MacroLoadNecRegisterFromFile(fp,NEC_IRQ_STATE);
fread(IRAM, sizeof(BYTE), 0x10000, fp);
fread(IO, sizeof(BYTE), 0x100, fp);
for (i =0; i < RAMBanks; i++)
{
if (RAMSize < 0x10000)
{
fread(RAMMap[i], 1, RAMSize, fp);
}
else
{
fread(RAMMap[i], 1, 0x10000, fp);
}
}
fread(Palette, sizeof(WORD), 16 * 16, fp);
fclose(fp);
WriteIO(0xC1, IO[0xC1]);
WriteIO(0xC2, IO[0xC2]);
WriteIO(0xC3, IO[0xC3]);
WriteIO(0xC0, IO[0xC0]);
for (i = 0x80; i <= 0x90; i++)
{
WriteIO(i, IO[i]);
}
}
void
WriteEC8 (
UINT8 Address,
UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(UINT16)(BIT0);
WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
}
/**
* WriteEC8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
*
*/
VOID
WriteEC8 (
IN UINT8 Address,
IN UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
void SimulatorIMP::evictMonoliths(Algorithm alg) {
for(auto& tp : tpacks) {
auto newPostings = tp.evictAll();
auto& segments = tp.unsafeGetSegments();
segments.clear();
segments.push_back(newPostings);
}
//consolidation cost is calc. here...
monolithicSegments.push_back(postingsInUpdateBuffer);
totalSeenPostings += postingsInUpdateBuffer;
postingsInUpdateBuffer = 0;
auto offset = (LogMerge == alg) ? offsetOfTelescopicMerge(monolithicSegments) :
(monolithicSegments.size() > 1 ? 0 : 1);
//override for NeverMerge
if(NeverMerge == alg) offset = monolithicSegments.size()-1;
assert(offset<=monolithicSegments.size());
if(offset<monolithicSegments.size()-1)
merges += consolidateSegments(monolithicSegments, offset);
else
merges += WriteIO(monolithicSegments.back(),1);
//fix segment sizes for tpacks (this how we know during queries how many seeks to make)
unsigned currentSzAll = monolithicSegments.size();
for(auto& tp : tpacks)
tp.unsafeGetSegments().resize(currentSzAll);
}
void
WritePMIO (
UINT8 Address,
UINT8 OpFlag,
void* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
for (i=0;i<=OpFlag;i++){
WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
}
}
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID
WritePMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1
}
}
ConsolidationStats consolidateTPStatic(TermPack& tp) {
auto &segments = tp.unsafeGetSegments();
auto offset = offsetOfTelescopicMerge(segments);
assert(offset<=monolithicSegments.size());
if(offset<monolithicSegments.size()-1)
return consolidateSegments(segments, offset);
ConsolidationStats nil;
nil += WriteIO(segments.back(),1);
return nil;
}
VOID
TraceCode (
IN UINT32 Level,
IN UINT32 Code
)
{
if ( ! (Level & CIM_DEBUG_LEVEL) ) {
return;
}
#if CIM_DEBUG & 1
if ( Code != 0xFF ) {
WriteIO (0x80, AccWidthUint8, &Code);
}
#endif
}
void
ReadPMIO2 (
UINT8 Address,
UINT8 OpFlag,
void* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
for (i=0;i<=OpFlag;i++){
WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
}
}
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
}
}
void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
UINT32 ddVar0;
UINT8 dbPortNum, dbVar0;
UINT32 dwIoBase, dwVar0;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
for (dbPortNum=0;dbPortNum<4;dbPortNum++){
ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
if ( ( ddVar0 & 0x0F ) == 0x03){
if ( dbPortNum & BIT0)
//this port belongs to secondary channel
ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
else
//this port belongs to primary channel
ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
if (pConfig->SataClass == LEGACY_IDE_MODE)
dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
if ( dbPortNum & BIT1)
//this port is slave
dbVar0=0xB0;
else
//this port is master
dbVar0=0xA0;
dwIoBase &= 0xFFF8;
WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
//Wait in loop for 30s for the drive to become ready
for (dwVar0=0;dwVar0<3000;dwVar0++){
ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
if ( (dbVar0 & 0x88) == 0)
break;
Stall(10000);
}
} //end of if ( ( ddVar0 & 0x0F ) == 0x03)
} //for (dbPortNum=0;dbPortNum<4;dbPortNum++)
} //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
}
/**
* Read Southbridge CIMx configuration structure pointer
*
*
*
* @retval 0xXXXXXXXX CIMx configuration structure pointer.
*
*/
AMDSBCFG*
getConfigPointer (
OUT VOID
)
{
UINT8 dbReg;
UINT8 dbValue;
UINT8 i;
UINT32 ddValue;
ddValue = 0;
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
ddValue |= (dbValue << (i * 8));
dbReg++;
}
return ( (AMDSBCFG*) (UINTN)ddValue);
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
}
}
}
if ( dbEnableAzalia ) {
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
//atleast one azalia codec found
// ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux
//ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
// dbChannelNum = 3;
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
//No Azalia codec found
if ( pConfig->AzaliaController != 2 ) {
int
ChannelInput (agc_t *State)
{
static int SocketInterlace = 0;
int i, j, k;
unsigned char c;
Client_t *Client;
int Channel, Value;
//We use SocketInterlace to slow down the number
// of polls of the sockets.
if (SocketInterlace > 0)
SocketInterlace--;
else
{
SocketInterlace = SocketInterlaceReload;
for (i = 0, Client = Clients; i < MAX_CLIENTS; i++, Client++)
if (Client->Socket != -1)
{
// We arbitrarily adopt the rule that we'll process at most one
// packet per client per instruction cycle.
for (j = Client->Size; j < 4; j++)
{
k = recv (Client->Socket, (char *) &c, 1, 0);
if (k == 0 || k == -1)
break;
// 20090318 RSB. Added this filter for a little robustness,
// but it shouldn't be needed.
if (!(
(Signatures[j] == (c & 0xC0)) ||
(DebugDeda && (SignaturesAgs[j] == (c & 0xC0)))
)
)
{
Client->Size = 0;
if (0 != (c & 0xC0))
{
j = -1;
continue;
}
j = 0;
}
Client->Packet[Client->Size++] = c;
}
// Process a received packet.
if (Client->Size >= 4)
{
int uBit, Type, Data;
//printf ("Received from %d: %02X %02X %02X %02X\n",
// i, Client->Packet[0], Client->Packet[1],
// Client->Packet[2], Client->Packet[3]);
if (!ParseIoPacket (Client->Packet, &Channel, &Value, &uBit))
{
// Convert to AGC format (upper 15 bits).
Value &= 077777;
if (uBit)
{
Client->ChannelMasks[Channel] = Value;
}
else if (Channel & 0x80)
{
// In this case we're dealing with a counter increment.
// So increment the counter.
//printf ("Channel=%02o Int=%o\n", Channel, Value);
UnprogrammedIncrement (State, Channel, Value);
Client->Size = 0;
return (1);
}
else
{
Value &= Client->ChannelMasks[Channel];
Value |=
ReadIO (State,
Channel) & ~Client->ChannelMasks[Channel];
WriteIO (State, Channel, Value);
// If this is a keystroke from the DSKY, generate an interrupt req.
if (Channel == 015)
State->InterruptRequests[5] = 1;
// If this is on fictitious input channel 0173, then the data
// should be placed in the INLINK counter register, and an
// UPRUPT interrupt request should be set.
else if (Channel == 0173)
{
State->Erasable[0][RegINLINK] = (Value & 077777);
State->InterruptRequests[7] = 1;
}
// Fictitious registers for rotational hand controller (RHC).
// Note that the RHC angles are not immediately used, but
// merely squirreled away for later. They won't actually
// go into the counter registers until the RHC counters are
// enabled and the data requested (bits 8,9 of channel 13).
else if (Channel == 0166)
{
LastRhcPitch = Value;
ChannelOutput (State, Channel, Value); // echo
}
else if (Channel == 0167)
{
LastRhcYaw = Value;
ChannelOutput (State, Channel, Value); // echo
}
else if (Channel == 0170)
{
LastRhcRoll = Value;
ChannelOutput (State, Channel, Value); // echo
}
else if (Channel == 031)
{
static int LastInDetent = 040000;
int InDetent;
ChannelOutput (State, Channel, Value);
// If the RHC stick has moved out of detent,
// generate a RUPT10 interrupt.
InDetent = (040000 & Value);
if (LastInDetent && !InDetent)
State->InterruptRequests[10] = 1;
LastInDetent = InDetent;
}
//---------------------------------------------------------------
// For --debug-dsky mode.
if (DebugDsky)
{
if (Channel == 032)
{
// For DebugDsky purposes only, the PRO key is translated
// to appear as the otherwise-fictitious KeyCode 0.
if (0 != (Value & 020000))
{
Channel = 015;
Value = 0;
}
}
if (Channel == 015)
{
int i, CurrentValue;
Value &= 077777;
for (i = 0; i < NumDebugRules; i++)
if (Value == DebugRules[i].KeyCode)
{
CurrentValue =
CurrentChannelValues[DebugRules[i].
Channel];
switch (DebugRules[i].Logic)
{
case '=':
CurrentValue = DebugRules[i].Value;
break;
case '|':
CurrentValue |= DebugRules[i].Value;
break;
case '&':
CurrentValue &= DebugRules[i].Value;
break;
case '^':
CurrentValue ^= DebugRules[i].Value;
break;
default:
break;
}
CurrentChannelValues[DebugRules[i].
Channel] =
CurrentValue;
ChannelOutput (State,
DebugRules[i].Channel,
CurrentValue);
}
}
//if (Channel != 032 && Channel != 015)
// WriteIO (State, Channel, Value);
}
//---------------------------------------------------------------
}
}
else if (DebugDeda && !ParseIoPacketAGS (Client->Packet, &Type, &Data))
{
// The following code is present only for debugging yaDEDA
// communications, and has no interesting purpose yaAGC-wise.
static unsigned char Buffer[9];
static int NumInBuffer = 0, NumWanted = 0, Collecting = 0;
static unsigned char Packet[4];
if (Type == 05 && (Data == 0777002 || Data == 0777004 ||
Data == 0777010 || Data == 0777020))
printf ("DEDA key release.\n");
else if (Collecting && Type == 07)
{
Buffer[NumInBuffer++] = Data >> 13;
if (NumInBuffer < NumWanted)
send (Client->Socket, (const char *) Packet, 4, 0);
else
{
int i;
Collecting = 0;
printf ("Received %d DEDA nibbles:", NumWanted);
for (i = 0; i < NumWanted; i++)
printf (" %1X", Buffer[i]);
printf ("\n");
if (NumWanted == 3)
{
if (!DedaQuiet)
DedaMonitor = 1;
DedaAddress = Buffer[0] * 0100 + Buffer[1] * 010 + Buffer[2];
DedaWhen = State->CycleCounter;
}
}
}
else if (Type == 05 && (Data == 0775002 || Data == 0773004))
{
NumInBuffer = 0;
Collecting = 1;
if (Data == 0775002)
{
printf ("Received DEDA READOUT.\n");
NumWanted = 3;
}
else
{
printf ("Received DEDA ENTR.\n");
NumWanted = 9;
}
FormIoPacketAGS (040, ~010, Packet);
send (Client->Socket, (const char *) Packet, 4, 0);
}
else if (Type == 05 && Data == 0767010)
{
printf ("Received DEDA HOLD.\n");
DedaMonitor = 0;
}
else if (Type == 05 && Data == 0757020)
{
printf ("Received DEDA CLR.\n");
DedaMonitor = 0;
}
else
printf ("Unknown AGS packet %02X %02X %02X %02X\n",
Client->Packet[0], Client->Packet[1],
Client->Packet[2], Client->Packet[3]);
}
Client->Size = 0;
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
}
}
}
if ( dbEnableAzalia ) {
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 0);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 2);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 4);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 6);
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
//atleast one azalia codec found
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
