/**
* FchSataBar5settingFpga
*
* @param[in] LocalCfgPtr
* @param[in] Bar5
*
*/
VOID
FchSataBar5settingFpga (
IN FCH_DATA_BLOCK *LocalCfgPtr,
IN UINT32 *Bar5
)
{
UINT8 Value;
//Get BAR5 value
ReadPci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
//Assign temporary BAR if is not already assigned
if ( (*Bar5 == 0) || (*Bar5 == - 1) ) {
//assign temporary BAR5
if ( (LocalCfgPtr->Sata.TempMMIO == 0) || (LocalCfgPtr->Sata.TempMMIO == - 1) ) {
*Bar5 = 0xFEC01000;
} else {
*Bar5 = LocalCfgPtr->Sata.TempMMIO;
}
WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + FCH_SATA_REG24), AccWidthUint32, Bar5);
}
//Clear Bits 9:0
*Bar5 = *Bar5 & 0xFFFFFC00;
Value = 0x07;
WritePci (((SATA_BUS_DEV_FUN_FPGA << 16) + 0x04), AccWidthUint8, &Value);
WritePci (((PCIB_BUS_DEV_FUN << 16) + 0x04), AccWidthUint8, &Value);
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT32 Bar5;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SataBar5setting (LocalCfgPtr, &Bar5);
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018A00, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0xFF, 0x01018F00, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, KERN_FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x07, StdHeader);
// Clear AHCI Enable during POST time. DE is investigating when/how to restore this bit before goes to OS boot.
RwMem ((Bar5 + FCH_SATA_BAR5_REG04), AccessWidth32, ~(UINT32) (BIT31), 0);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG04), AccessWidth32, 0xFFFFFFFF, 0x00, StdHeader);
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
/**
* FchInitLatePcib - Prepare Pcib controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLatePcib (
IN VOID *FchDataPtr
)
{
UINT8 Value;
UINT8 NStBit;
UINT8 NSBit;
UINT32 VarDd;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// We need to do the following setting in late post also because some bios core pci enumeration changes these values
// programmed during early post.
// Master Latency Timer
//
Value = 0x40;
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader);
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader);
//
// CLKRUN#
// FCH P2P AutoClock control settings.
// VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow);
//
if ( LocalCfgPtr->Pcib.PcibClockRun ) {
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value);
NStBit = Value & 0x03;
NSBit = (Value & 0x3F ) >> 2;
VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
VarDd = 9; // for A12
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader);
}
/**
* FchInitEnvSataIde - Config SATA IDE controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde (
IN VOID *FchDataPtr
)
{
UINT8 ChannelByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018A40, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
}
//
// Device ID
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_DID, StdHeader);
//
// SSID
//
if (LocalCfgPtr->Sata.SataIdeSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataIdeSsid, StdHeader);
}
//
// Sata IDE Channel configuration
//
ChannelByte = 0x00;
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
ChannelByte &= 0xCF;
if ( LocalCfgPtr->Sata.SataDisUnusedIdePChannel ) {
ChannelByte |= 0x10;
}
if ( LocalCfgPtr->Sata.SataDisUnusedIdeSChannel ) {
ChannelByte |= 0x20;
}
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, &ChannelByte, StdHeader);
}
/**
* EnableEhciController - Assign resources and enable EHCI controllers
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] BarAddress Base address for Ehci controller
* @param[in] StdHeader AMD standard header config param
*/
VOID
EnableEhciController (
IN UINT32 Value,
IN UINT32 BarAddress,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Var;
WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1 + BIT2, StdHeader);
ReadPci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
if ( (BarAddress != - 1) && (BarAddress != 0) ) {
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader);
Var = 0x00020F00;
WriteMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, &Var);
RwMem (BarAddress + FCH_EHCI_BAR_REGA4, AccessWidth32, 0xFF00FF00, 0x00400040);
RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, ~( BIT12 + BIT14), BIT12 + BIT14);
RwMem (BarAddress + FCH_EHCI_BAR_REGB0, AccessWidth32, ~BIT5, BIT5);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth16, ~BIT12, BIT12);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF0, AccessWidth32, ~BIT16, BIT16);
RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~BIT12, BIT12);
RwMem (BarAddress + FCH_EHCI_BAR_REGC4, AccessWidth32, (UINT32) (~ 0x00000f00), 0x00000200);
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0000ff00), 0x00000f00);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 17)), (UINT32) (0x01 << 17), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 21)), (UINT32) (0x01 << 21), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50, AccessWidth32, ~ ((UINT32) (0x01 << 29)), (UINT32) (0x01 << 29), StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, (UINT16)0xFFFF, BIT16 + BIT10, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~ (BIT0 + (3 << 5) + (7 << 7)), 0x0000026b, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT4, BIT4, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth32, ~BIT11, BIT11, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54, AccessWidth16, (UINT16)0x5FFF, BIT13 + BIT15, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG50 + 2, AccessWidth16, ~BIT3, BIT3, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFC, BIT0 + BIT1, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFFB, BIT2, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG54 + 2, AccessWidth16, (UINT16)0xFFF7, BIT3, StdHeader);
}
}
/**
* sataBar5setting - Config SATA BAR5
*
*
* @param[in] FchDataPtr - Fch configuration structure pointer.
* @param[in] *Bar5Ptr - SATA BAR5 buffer.
*
*/
VOID
SataBar5setting (
IN VOID *FchDataPtr,
IN UINT32 *Bar5Ptr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Get BAR5 value
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
//
//Assign temporary BAR if is not already assigned
//
if ( (*Bar5Ptr == 0) || (*Bar5Ptr == - 1) ) {
//
//assign temporary BAR5
//
if ( (LocalCfgPtr->Sata.TempMmio == 0) || (LocalCfgPtr->Sata.TempMmio == - 1) ) {
*Bar5Ptr = 0xFEC01000;
} else {
*Bar5Ptr = LocalCfgPtr->Sata.TempMmio;
}
WritePci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG24), AccessWidth32, Bar5Ptr, StdHeader);
}
//
//Clear Bits 9:0
//
*Bar5Ptr = *Bar5Ptr & 0xFFFFFC00;
}
/**
* FchInitLateSata - Prepare SATA controller to boot to OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSata (
IN VOID *FchDataPtr
)
{
UINT8 SataPciCommandByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Return immediately is sata controller is not enabled
//
if ( LocalCfgPtr->Sata.SataMode.SataEnable == 0 ) {
return;
}
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
//
// Set Sata Controller Memory & IO access enable
//
ReadPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, 0xFF, 0x03, StdHeader);
//
// Call Sub-function for each Sata mode
//
if (( LocalCfgPtr->Sata.SataClass == SataAhci7804) || (LocalCfgPtr->Sata.SataClass == SataAhci )) {
FchInitLateSataAhci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataIde2Ahci) || (LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 )) {
FchInitLateSataIde2Ahci ( LocalCfgPtr );
}
if (( LocalCfgPtr->Sata.SataClass == SataNativeIde) || (LocalCfgPtr->Sata.SataClass == SataLegacyIde )) {
FchInitLateSataIde ( LocalCfgPtr );
}
if ( LocalCfgPtr->Sata.SataClass == SataRaid) {
FchInitLateSataRaid ( LocalCfgPtr );
}
FchInitLateProgramSataRegs ( LocalCfgPtr );
//
// Restore Sata Controller Memory & IO access status
//
WritePci (((SATA_BUS_DEV_FUN << 16) + 0x04), AccessWidth8, &SataPciCommandByte, StdHeader);
//
// Set Sata PCI Configuration Space Write disable
//
SataDisableWriteAccess (StdHeader);
}
/**
* FchInitResetHwAcpi - Config HwAcpi controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpi (
IN VOID *FchDataPtr
)
{
UINT16 SmbusBase;
UINT8 Value;
UINT16 AsfPort;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set Build option into SB
//
WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader);
//
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1]
SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress);
Value = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
//
// Prevent RTC error
//
Value = 0x0A;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xEF;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value | 0x0A;
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value & 0xF9;
}
if ( LocalCfgPtr->LegacyFree ) {
//
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
//
Value = Value & 0x9F;
}
//
// Enabled IRQ input
//
Value = Value | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0);
if ( AsfPort != 0 ) {
UINT8 dbValue;
dbValue = 0x70;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
}
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchXhciInitIndirectReg (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = (UINT32) (LocalCfgPtr->Usb.Xhci20Phy[Port]);
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, ((Port - 2) << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
if ( ReadFchChipsetRevision ( StdHeader ) >= FCH_BOLTON ) {
// RRG 8.36 Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(UINT32) (BIT23), BIT23);
// RPR 8.61 XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
} else {
ReadXhci1Phy ((Port - 2), (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, ((Port - 2) << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
//8.64 L1 Residency Duration
RwXhciIndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
* @param[in] FchRevision FCH Chip revision
*
*/
VOID
FchXhciRecoveryInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT8 FchRevision
)
{
UINT8 Index;
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT32 Xhci20Phy[MAX_XHCI_PORTS];
Xhci20Phy[0] = 0x21;
Xhci20Phy[1] = 0x21;
Xhci20Phy[2] = 0x24;
Xhci20Phy[3] = 0x24;
DrivingStrength = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = (UINT32) (Xhci20Phy[Port]);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader);
// RPR 8.25 Clock Gating in PHY
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = 0x1E4;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
}
// Enhance XHC LS Rise time
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1C4;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + DrivingStrength, StdHeader);
}
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccessWidth32, ~(BIT23), BIT23);
// XHCI ISO device CRC false error detection
for (Port = 0; Port < 4; Port ++) {
if (Port < 2) {
ReadXhci0Phy (Port, (0x7 << 7), &DrivingStrength, StdHeader);
DrivingStrength &= 0x0000000F8;
DrivingStrength |= BIT0 + BIT2;
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + (0x7 << 7) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + (0x7 << 7) + DrivingStrength, StdHeader);
}
}
// L1 Residency Duration
RwXhci0IndReg ( FCH_XHCI_IND60_REG48, 0xFFFFFFFE0, BIT0, StdHeader);
}
/**
* FchInitResetXhciProgram - Config Xhci controller during
* Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetXhciProgram (
IN VOID *FchDataPtr
)
{
UINT8 IndexValue;
UINT32 ValueDword;
UINT8 ValueByte;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
if ( ValueDword == (FCH_USB_XHCI_DID << 16) + FCH_USB_XHCI_VID) {
//
// First Xhci controller.
//
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ValueDword = 0;
IndexValue = XHCI_REGISTER_BAR00;
ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
IndexValue = XHCI_REGISTER_04H;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI_REGISTER_0CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI_REGISTER_3CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
//
// Second Xhci controller.
//
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccessWidth32, &ValueDword, StdHeader);
ValueDword = 0;
IndexValue = XHCI1_REGISTER_BAR00;
ReadBiosram (IndexValue, AccessWidth32, &ValueDword, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccessWidth32, &ValueDword, StdHeader);
IndexValue = XHCI1_REGISTER_04H;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI1_REGISTER_0CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccessWidth8, &ValueByte, StdHeader);
IndexValue = XHCI1_REGISTER_3CH;
ReadBiosram (IndexValue, AccessWidth8, &ValueByte, StdHeader);
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccessWidth8, &ValueByte, StdHeader);
}
}
/**
* FchXhciInitIndirectReg - Config XHCI Indirect Registers
*
*
*
* @param[in] StdHeader AMD Standard Header
*
*/
VOID
FchXhciInitIndirectReg (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 DrivingStrength;
UINT32 Port;
UINT32 Register;
UINT32 RegValue;
UINT8 Index;
DrivingStrength = 0;
Port = 0;
//
// SuperSpeed PHY Configuration (adaptation mode setting)
//
RwXhciIndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
//
// SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RwXhciIndReg ( FCH_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A, StdHeader);
RwXhciIndReg ( FCH_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A, StdHeader);
//
// BLM Meaasge
//
RwXhciIndReg ( FCH_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000, StdHeader);
//
// xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (Port = 0; Port < 4; Port ++) {
DrivingStrength = BIT2;
if (Port < 2) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, (Port << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
} else {
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE1E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFE0E78, ((Port - 2) << 13) + BIT8 + BIT7 + DrivingStrength, StdHeader);
Register = FCH_XHCI_IND60_REG00;
Index = 0;
do {
WritePci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccessWidth32, &Register, StdHeader);
ReadPci ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccessWidth32, &RegValue, StdHeader);
Index++;
FchStall (10, StdHeader);
} while ((RegValue & BIT17) && (Index < 10 ));
RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000, StdHeader);
}
}
// Step 3
RwXhciIndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhciIndReg ( FCH_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)), StdHeader);
}
/**
* FchInitResetHwAcpi - Config HwAcpi controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpi (
IN VOID *FchDataPtr
)
{
UINT16 SmbusBase;
UINT8 Value;
UINT16 AsfPort;
UINT32 GeventEnableBits;
UINT32 GeventValue;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set Build option into SB
//
WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.FchBldCfg->CfgSioPmeBaseAddress), StdHeader);
//
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.FchBldCfg->CfgSmbus1BaseAddress) + BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgCpuControlBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.FchBldCfg->CfgSmiCmdPortAddr) + 8);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.FchBldCfg->CfgWatchDogTimerBase));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, (UINT32)~(BIT1 + BIT2), 0); ///clear BIT[2:1]
SmbusBase = (UINT16) (UserOptions.FchBldCfg->CfgSmbus0BaseAddress);
Value = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
if (UserOptions.FchBldCfg->CfgFchGpioControl != NULL) {
ProgramFchGpioTbl ((UserOptions.FchBldCfg->CfgFchGpioControl), LocalCfgPtr);
}
if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
}
//
// RTC Workaround for Daylight saving time enable bit
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable
Value = 0x0B;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xFE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable
//
// Prevent RTC error
//
Value = 0x0A;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xEF;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value | 0x0A;
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) {
Value = RTC_WORKAROUND_SECOND;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
if ( Value > RTC_VALID_SECOND_VALUE ) {
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= RTC_SECOND_LOWER_NIBBLE;
if ( Value > RTC_VALID_SECOND_VALUE_LN ) {
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
}
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value & 0xF9;
}
if ( LocalCfgPtr->LegacyFree ) {
//
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
//
Value = Value & 0x9F;
}
//
// Enabled IRQ input
//
Value = Value | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
AsfPort = ((UINT16) UserOptions.FchBldCfg->CfgSmbus1BaseAddress & 0xFFF0);
if ( AsfPort != 0 ) {
UINT8 dbValue;
dbValue = 0x70;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
dbValue = 0x2F;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0A, &dbValue, StdHeader);
}
//
// PciExpWakeStatus workaround
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
AsfPort++;
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits);
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue);
if ( (GeventValue & GeventEnableBits) != 0 ) {
Value = 0x40;
LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
}
LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader);
if ((Value & (BIT2 + BIT0)) != 0) {
Value = 0x40;
LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
}
//
// Set ACPIMMIO by OEM Input table
//
if ( LocalCfgPtr->OemResetProgrammingTablePtr != NULL ) {
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->OemResetProgrammingTablePtr), StdHeader);
}
}
/**
* FchInitLateGpp - Prepare Gpp controller to boot to OS.
*
* PcieGppLateInit
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateGpp (
IN VOID *FchDataPtr
)
{
UINT8 PortId;
UINT8 BusNum;
UINT8 AspmValue;
UINT8 PortAspmValue;
UINT8 AllowStrapControlByAB;
UINT8 FchGppPhyPllPowerDown;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT32 PciAspmValue;
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Disable hidden register decode and serial number capability
//
AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader);
WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader);
if (ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader) & BIT8) {
return;
}
//
// Configure ASPM
//
AspmValue = (UINT8)LocalCfgPtr->Gpp.GppPortAspm;
FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
AllowStrapControlByAB = 0x01;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
//
// write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS
// when native PCIE is enabled but MSI is not available
// BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
//
PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
if (PortCfg->PortHotPlug) {
RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang
}
WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader);
ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader);
if (BusNum != 0xFF) {
ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader);
if (PciAspmValue != 0xffffffff) {
PortAspmValue = AspmValue;
//
// Validate ASPM support on EP side
//
FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader);
//
// Set ASPM on EP side
//
FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader);
//
// Set ASPM on port side
//
FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader);
}
}
RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (PortId << 24) ), ~(BIT15), (BIT15), StdHeader);
}
RwAlink ((FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0), StdHeader);
//
// Configure Lock HWInit registers
//
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
if (AbValue & 0xF0) {
AbValue = ReadAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), StdHeader);
WriteAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK
if ( FchGppPhyPllPowerDown == TRUE ) {
//
// Power Saving Feature for GPP Lanes
//
// Set PCIE_P_CNTL in Alink PCIEIND space
//
AbValue = ReadAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), StdHeader);
AbValue |= BIT12 + BIT3 + BIT0;
AbValue &= ~(BIT9 + BIT4);
WriteAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT8), (BIT8), StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT3), (BIT3), StdHeader);
}
}
//
// Restore strap0 via override
//
if (LocalCfgPtr->Gpp.PcieAer) {
RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
RwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
}
}