bool BdPortInit(uint32 * BaseAddress, uint32 BaudRate)
{
#define PADCONF_CTS ((1 << 4) | (1 << 3) | (1 << 8))
#define PADCONF_RTS (0)
#define PADCONF_TX (0)
#define PADCONF_RX ((1 << 3) | (1 << 8))
uartBase = BaseAddress;
uint8 * HalpSCM = (uint8 *)OMAP_SCM_BASE;
uint8 * HalpCORE_CM = (uint8 *)OMAP_CORE_CM_BASE;
uint32 Value;
if (BaseAddress == (uint32 *)OMAP_UART1_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART1;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
// Configure uart1 pads per documentation example
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_TX,
PADCONF_TX | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART1_CTS,
PADCONF_CTS | (PADCONF_RX << 16));
}
else if (BaseAddress == (uint32 *)OMAP_UART2_BASE) {
// Power on the required function and interface units.
Value = ReadReg32(HalpCORE_CM + CM_FCLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_FCLKEN1_CORE, Value);
Value = ReadReg32(HalpCORE_CM + CM_ICLKEN1_CORE);
Value |= CM_CORE_EN_UART2;
WriteReg32(HalpCORE_CM + CM_ICLKEN1_CORE, Value);
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_CTS,
PADCONF_CTS | (PADCONF_RTS << 16));
WriteReg32(HalpSCM + OMAP_CONTROL_PADCONF_UART2_TX,
PADCONF_TX | (PADCONF_RX << 16));
}
// Set the default baudrate.
UartSetBaudRate(BaseAddress, BaudRate);
// Set DLAB to zero. DLAB controls the meaning of the first two
// registers. When zero, the first register is used for all byte transfer
// and the second register controls device interrupts.
//
WriteReg8(BaseAddress + COM_LCR,
ReadReg8(BaseAddress + COM_LCR) & ~LCR_DLAB);
// Disable device interrupts. This implementation will handle state
// transitions by request only.
//
WriteReg8(BaseAddress + COM_IEN, 0);
// Reset and disable the FIFO queue.
// N.B. FIFO will be reenabled before returning from this routine.
//
WriteReg8(BaseAddress + COM_FCR, FCR_CLEAR_TRANSMIT | FCR_CLEAR_RECEIVE);
// Configure the Modem Control Register. Disabled device interrupts,
// turn off loopback.
//
WriteReg8(BaseAddress + COM_MCR,
ReadReg8(BaseAddress + COM_MCR) & MCR_INITIALIZE);
// Initialize the Modem Control Register. Indicate to the device that
// we are able to send and receive data.
//
WriteReg8(BaseAddress + COM_MCR, MCR_INITIALIZE);
// Enable the FIFO queues.
WriteReg8(BaseAddress + COM_FCR, FCR_ENABLE);
return true;
}
static void
Virge_WriteMode(const DisplayModeEx& mode, VirgeRegRec& regRec)
{
// This function writes out all of the standard VGA and extended S3 registers
// needed to setup a video mode.
TRACE("Virge_WriteMode()\n");
SharedInfo& si = *gInfo.sharedInfo;
// First reset GE to make sure nothing is going on.
if (ReadCrtcReg(si.chipType == S3_VIRGE_VX ? 0x63 : 0x66) & 0x01)
Virge_GEReset(mode);
// As per databook, always disable STREAMS before changing modes.
if ((ReadCrtcReg(0x67) & 0x0c) == 0x0c) {
// STREAMS running, disable it
VerticalRetraceWait();
WriteReg32(FIFO_CONTROL_REG, 0xC000);
WriteCrtcReg(0x67, 0x00, 0x0c); // disable STREAMS processor
}
// Restore S3 extended regs.
WriteCrtcReg(0x63, regRec.CR63);
WriteCrtcReg(0x66, regRec.CR66);
WriteCrtcReg(0x3a, regRec.CR3A);
WriteCrtcReg(0x31, regRec.CR31);
WriteCrtcReg(0x58, regRec.CR58);
// Extended mode timings registers.
WriteCrtcReg(0x53, regRec.CR53);
WriteCrtcReg(0x5d, regRec.CR5D);
WriteCrtcReg(0x5e, regRec.CR5E);
WriteCrtcReg(0x3b, regRec.CR3B);
WriteCrtcReg(0x3c, regRec.CR3C);
WriteCrtcReg(0x43, regRec.CR43);
WriteCrtcReg(0x65, regRec.CR65);
WriteCrtcReg(0x6d, regRec.CR6D);
// Restore the desired video mode with CR67.
WriteCrtcReg(0x67, 0x50, 0xf0); // possible hardware bug on VX?
snooze(10000);
WriteCrtcReg(0x67, regRec.CR67 & ~0x0c); // Don't enable STREAMS
// Other mode timing and extended regs.
WriteCrtcReg(0x34, regRec.CR34);
if (si.chipType != S3_TRIO_3D && si.chipType != S3_VIRGE_MX) {
WriteCrtcReg(0x40, regRec.CR40);
}
if (S3_VIRGE_MX_SERIES(si.chipType)) {
WriteCrtcReg(0x41, regRec.CR41);
}
WriteCrtcReg(0x42, regRec.CR42);
WriteCrtcReg(0x45, regRec.CR45);
WriteCrtcReg(0x51, regRec.CR51);
WriteCrtcReg(0x54, regRec.CR54);
// Memory timings.
WriteCrtcReg(0x68, regRec.CR68);
WriteCrtcReg(0x69, regRec.CR69);
WriteCrtcReg(0x33, regRec.CR33);
if (si.chipType == S3_TRIO_3D_2X || S3_VIRGE_GX2_SERIES(si.chipType)
/* MXTESTME */ || S3_VIRGE_MX_SERIES(si.chipType) ) {
WriteCrtcReg(0x85, regRec.CR85);
}
if (si.chipType == S3_VIRGE_DXGX) {
WriteCrtcReg(0x86, regRec.CR86);
}
if ( (si.chipType == S3_VIRGE_GX2) || S3_VIRGE_MX_SERIES(si.chipType) ) {
WriteCrtcReg(0x7b, regRec.CR7B);
WriteCrtcReg(0x7d, regRec.CR7D);
WriteCrtcReg(0x87, regRec.CR87);
WriteCrtcReg(0x92, regRec.CR92);
WriteCrtcReg(0x93, regRec.CR93);
}
if (si.chipType == S3_VIRGE_DXGX || S3_VIRGE_GX2_SERIES(si.chipType) ||
S3_VIRGE_MX_SERIES(si.chipType) || si.chipType == S3_TRIO_3D) {
WriteCrtcReg(0x90, regRec.CR90);
WriteCrtcReg(0x91, regRec.CR91);
}
WriteSeqReg(0x08, 0x06); // unlock extended sequencer regs
// Restore extended sequencer regs for DCLK.
WriteSeqReg(0x12, regRec.SR12);
WriteSeqReg(0x13, regRec.SR13);
if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType)) {
WriteSeqReg(0x29, regRec.SR29);
}
if (S3_VIRGE_MX_SERIES(si.chipType)) {
WriteSeqReg(0x54, regRec.SR54);
WriteSeqReg(0x55, regRec.SR55);
WriteSeqReg(0x56, regRec.SR56);
WriteSeqReg(0x57, regRec.SR57);
}
WriteSeqReg(0x18, regRec.SR18);
// Load new m,n PLL values for DCLK & MCLK.
uint8 tmp = ReadSeqReg(0x15) & ~0x21;
WriteSeqReg(0x15, tmp | 0x03);
WriteSeqReg(0x15, tmp | 0x23);
WriteSeqReg(0x15, tmp | 0x03);
WriteSeqReg(0x15, regRec.SR15);
if (si.chipType == S3_TRIO_3D) {
WriteSeqReg(0x0a, regRec.SR0A);
WriteSeqReg(0x0f, regRec.SR0F);
}
// Now write out CR67 in full, possibly starting STREAMS.
VerticalRetraceWait();
WriteCrtcReg(0x67, 0x50); // For possible bug on VX?!
snooze(10000);
WriteCrtcReg(0x67, regRec.CR67);
uint8 cr66 = ReadCrtcReg(0x66);
WriteCrtcReg(0x66, cr66 | 0x80);
WriteCrtcReg(0x3a, regRec.CR3A | 0x80);
// Now, before we continue, check if this mode has the graphic engine ON.
// If yes, then we reset it.
if (si.chipType == S3_VIRGE_VX) {
if (regRec.CR63 & 0x01)
Virge_GEReset(mode);
} else {
if (regRec.CR66 & 0x01)
Virge_GEReset(mode);
}
VerticalRetraceWait();
if (S3_VIRGE_GX2_SERIES(si.chipType) || S3_VIRGE_MX_SERIES(si.chipType) ) {
WriteCrtcReg(0x85, 0x1f); // primary stream threshold
}
// Set the standard CRTC vga regs.
WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11
for (int j = 0; j < NUM_ELEMENTS(regRec.CRTC); j++) {
WriteCrtcReg(j, regRec.CRTC[j]);
}
// Setup HSYNC & VSYNC polarity and select clock source 2 (0x0c) for
// programmable PLL.
uint8 miscOutReg = 0x23 | 0x0c;
if (!(mode.timing.flags & B_POSITIVE_HSYNC))
miscOutReg |= 0x40;
if (!(mode.timing.flags & B_POSITIVE_VSYNC))
miscOutReg |= 0x80;
WriteMiscOutReg(miscOutReg);
WriteCrtcReg(0x66, cr66);
WriteCrtcReg(0x3a, regRec.CR3A);
return ;
}
void iep_config_done(void *base)
{
WriteReg32(base, rIEP_CONF_DONE, 1);
}