int main()
{
int status;
int temp,i,j;
//static int Result1[SIZE];
init_platform();
// Initialize DMA
init_dma();
//get data from the PL block to DDR RAM
status = XAxiDma_SimpleTransfer(&AxiDma, 0xa000000, 1023,XAXIDMA_DEVICE_TO_DMA);
/* Wait for transfer to be done */
while(XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA));
j=0;
// read data from DDR ram to UART
for(i=0;i<=1023;i+=1)
{
temp = Xil_In32(0xa000000+j);
xil_printf("DDR address 0x%x",0xa0000000+i);
xil_printf(" contains %d\n\r",temp);
j+=4;
}
return 0;
}
/**
* Sets bits contained in multiple LUTs specified by the coordinates and data in the lut_configs array.
*
* @return XST_SUCCESS or XST_FAILURE.
**/
int MiCAP_Custom_SetMultiClbBits(XGpio* gpio_InstancePtr, XAxiDma* dma_InstancePtr,LUT_config_type *lut_configs, u32 num_lut_configs) {
u8 bottom_ntop;
int Status;
int clock_row;
u32 major_frame_address;
u32 word_offset;
assert(num_lut_configs>0);
long slice_row = lut_configs[0].slice_row;
long slice_col = lut_configs[0].slice_col;
// Check if all the lutconfigs are indeed part of the same set of frames
u32 i;
for(i = 1; i<num_lut_configs; i++) {
if(!MiCAP_Custom_IsSameFrame(slice_row, slice_col, lut_configs[i].slice_row, lut_configs[i].slice_col))
return XST_FAILURE;
}
MiCAP_GetConfigurationCoordinates(slice_row, slice_col,
&bottom_ntop, &clock_row, &major_frame_address, &word_offset);
u32 frame_num = 4;
u32 frame_number_offset;
if(lut_configs[0].Resource[0][1] < 32)
frame_number_offset = 26;
else
frame_number_offset = 32;
u32 buffer[506];
u32 frame_address = XHwIcap_Custom_SetupFar7series(bottom_ntop, XHI_FAR_CLB_BLOCK, clock_row, major_frame_address, frame_number_offset);
u32 Read_frame_TxBuffer[] = {0xFFFFFFFF, 0xFFFFFFFF,0xAA995566, 0x20000000, 0x20000000, 0x30008001, 0x00000007,
0x20000000, 0x20000000, 0x30008001, 0x00000004, 0x20000000, 0x20000000,
0x20000000, 0x30002001, frame_address, 0x28006000, 0x480001FA, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000, 0x20000000,
0x20000000, 0x30008001, 0x0000000D, 0x20000000, 0x20000000,0xFFFFFFFF,
0xFFFFFFFF,0xFFFFFFFF};
memcpy(TxBufferPtr_rdFrame, Read_frame_TxBuffer, 57 * sizeof(u32));
// Frame Read:
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x4); // assert read ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x5); // assert read ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_rdFrame,
57*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x1)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//2) Reading the frames back
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) RxBufferPtr_rdFrame,
MAX_PKT_LEN_rdFrame, XAXIDMA_DEVICE_TO_DMA);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DEVICE_TO_DMA)) {
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0); // Put data source back in reset state for next run
Xil_DCacheFlushRange((u32)RxBufferPtr_rdFrame, 540*4);
u32 *configuration = buffer + 101 + 1 + 1;
for(i = 0; i< num_lut_configs; i++) {
u32 word_offset = MiCAP_Custom_GetWordOffset(lut_configs[i].slice_row);
MiCAP_Custom_SetClbBitsInConfig(configuration, word_offset,
frame_num, frame_number_offset, lut_configs[i].Resource, lut_configs[i].Value, lut_configs[i].NumBits);
}
//3: Frame Write
u32 head[] = {0xFFFFFFFF, 0xFFFFFFFF, 0x20000000, 0xAA995566, 0x20000000, 0x20000000,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30018001, 0x03727093,
0x30002001, frame_address, 0x30008001, 0x00000001, 0x20000000, 0x300041F9};
u32 tail[] = {0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30002001, 0x00061080,
0x30008001, 0x00000007, 0x20000000, 0x20000000, 0x30008001, 0x0000000D,
0x20000000, 0x20000000,0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF};
for (j=0; j<18; j++){
TxBufferPtr_wrFrame[j] = head[j];
}
for (i=0; i<505; i++){
TxBufferPtr_wrFrame[j] = configuration[i];
j++;
}
for (i=0; i<17;i++){
TxBufferPtr_wrFrame[j] = tail[i];
j++;
}
Xil_DCacheFlushRange((u32)TxBufferPtr_wrFrame, 540*4);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x0);
//Xil_DCacheFlushRange((u32)TxBufferPtr_rdFrame, MAX_PKT_LEN_rdFrame);
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x2); // assert write ctrl
//gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
while(!(gpio_stat & 0x4)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x3); // assert write ctrl + reset release
Status = XAxiDma_SimpleTransfer(dma_InstancePtr,(u32) TxBufferPtr_wrFrame,
540*4, XAXIDMA_DMA_TO_DEVICE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
while (XAxiDma_Busy(dma_InstancePtr,XAXIDMA_DMA_TO_DEVICE)) {
}
while(!(gpio_stat & 0x2)){
gpio_stat = XGpio_DiscreteRead(gpio_InstancePtr, 2);
}
XGpio_DiscreteWrite(gpio_InstancePtr, 1, 0x10);
return XST_SUCCESS;
}
void DMA_wait(void) {
while (XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE)) {
/* Wait */
}
}
/* Should be called after adc_fmc150_capture() */
int get_samples(u32 *size, u32 *byte_offset, struct low_level_handler *low_lev_handler)
{
int i;
s32 tmp_size = 1;
#ifdef LOW_LEV_DEBUG
xil_printf("get_samples: trying to get %d samples...\n", *size);
#endif
/*XAxiDma_Reset(&low_lev_handler->attr->AxiDma);
// Check if DMA has completed its reset
if(XAxiDma_ResetIsDone(&low_lev_handler->attr->AxiDma) == 0){
#ifdef LOW_LEV_DEBUG
xil_printf("DMA has not completed its reset!\n");
#endif
return ERROR;
}*/
/* Resume DMA transactions if halted */
/*if ((error = XAxiDma_Resume(&low_lev_handler->attr->AxiDma)) != XST_SUCCESS){
#ifdef LOW_LEV_DEBUG
xil_printf("DMA has not resumed! Error: %s\n", (error == XST_NOT_SGDMA) ? "XST_NOT_SGDMA" : "XST_DMA_ERROR");
#endif
return ERROR;
}
else{
#ifdef LOW_LEV_DEBUG
xil_printf("Enabling DMA interrupts\n");
#endif
Enable DMA interrupts
XAxiDma_IntrEnable(&low_lev_handler->attr->AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA);
}*/
/* Trying to read more than available in buffer */
if(low_lev_handler->samples_count_pos + *size > low_lev_handler->samples_count){
tmp_size = low_lev_handler->samples_count - low_lev_handler->samples_count_pos;
#ifdef LOW_LEV_DEBUG
xil_printf("get_samples: samples_count_pos = %d\n", low_lev_handler->samples_count_pos);
xil_printf("get_samples: samples_count = %d\n", low_lev_handler->samples_count);
xil_printf("get_samples: Size from adc_fmc150_get_samples trimmed to %d\n", tmp_size);
#endif
}
/* No more data to read from buffer! Issue a new capture from adc.
* Tricky construct*/
if(tmp_size <= 0 && (tmp_size = *size) && capture_samples(*size, low_lev_handler) < 0){
xil_printf("Could not acquire samples\n");
return ERROR;
}
/* FIX this! Decouple modules! and improve clarity*/
*size = (tmp_size > low_lev_handler->attr->max_resp_buffer_packets) ?
low_lev_handler->attr->max_resp_buffer_packets : tmp_size;
for(i = 0; i < MAX_DMA_TRIES; ++i){
if(XAxiDma_Busy(&low_lev_handler->attr->AxiDma, XAXIDMA_DEVICE_TO_DMA) != TRUE){
#ifdef LOW_LEV_DEBUG
xil_printf("get_samples: DMA has completed!\n");
#endif
break;
}
delay(1000);
}
if(i == MAX_DMA_TRIES){
#ifdef LOW_LEV_DEBUG
xil_printf("get_samples: DMA has failed to deliver data!\n");
#endif
//XAxiDma_Reset(&low_lev_handler->attr->AxiDma);
return ERROR;
}
/* Check for DMA errors explicitly */
//xil_printf("DMA ADC status reg: %08X\n", XIo_In32(BPM_ADC_DMA_BASEADDR + 0x034));
*byte_offset = low_lev_handler->samples_count_pos * low_lev_handler->attr->sample_size;
low_lev_handler->samples_count_pos += *size;
#ifdef LOW_LEV_DEBUG
xil_printf("get_samples: *byte_offset = %d\n", *byte_offset);
xil_printf("get_samples: samples_count_pos = %d\n", low_lev_handler->samples_count_pos);
xil_printf("get_samples: *size = %d\n", *size);
#endif
return SUCCESS;
}
