void delay_ms(unsigned int time) {
t = time;
XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
XPAR_XPS_TIMER_0_INTERRUPT_MASK |
XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
while (t > 1) {};
XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
//XPAR_XPS_TIMER_0_INTERRUPT_MASK |
XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
};
XStatus
init_ll_fifo(struct xemac_s *xemac)
{
xlltemacif_s *xlltemacif = (xlltemacif_s *)(xemac->state);
#if NO_SYS
struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
#endif
/* initialize ll fifo */
XLlFifo_Initialize(&xlltemacif->llfifo,
XLlTemac_LlDevBaseAddress(&xlltemacif->lltemac));
/* Clear any pending FIFO interrupts */
XLlFifo_IntClear(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
/* enable fifo interrupts */
XLlFifo_IntEnable(&xlltemacif->llfifo, XLLF_INT_ALL_MASK);
#if NO_SYS
/* Register temac interrupt with interrupt controller */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
/* connect & enable FIFO interrupt */
XIntc_RegisterHandler(xtopologyp->intc_baseaddr,
xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
/* Enable EMAC interrupts in the interrupt controller */
do {
/* read current interrupt enable mask */
unsigned int cur_mask = XIntc_In32(xtopologyp->intc_baseaddr + XIN_IER_OFFSET);
/* form new mask enabling SDMA & ll_temac interrupts */
cur_mask = cur_mask
| (1 << xlltemacif->lltemac.Config.LLFifoIntr)
| (1 << xlltemacif->lltemac.Config.TemacIntr);
/* set new mask */
XIntc_mEnableIntr(xtopologyp->intc_baseaddr, cur_mask);
} while (0);
#else
/* connect & enable TEMAC interrupts */
register_int_handler(xlltemacif->lltemac.Config.TemacIntr,
(XInterruptHandler)xlltemac_error_handler,
&xlltemacif->lltemac);
enable_interrupt(xlltemacif->lltemac.Config.TemacIntr);
/* connect & enable FIFO interrupts */
register_int_handler(xlltemacif->lltemac.Config.LLFifoIntr,
(XInterruptHandler)xllfifo_intr_handler,
xemac);
enable_interrupt(xlltemacif->lltemac.Config.LLFifoIntr);
#endif
return 0;
}
void init_all(void) {
XIntc_Initialize(&intc, XPAR_XPS_INTC_0_DEVICE_ID);
microblaze_enable_interrupts();
XIntc_mMasterEnable(XPAR_INTC_0_BASEADDR);
XUartLite_mEnableIntr(XPAR_UARTLITE_0_BASEADDR);
//// пецхярпюжхъ напюанрвхйнб ////////////////////////////////////////////
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_UARTLITE_0_VEC_ID,
(XInterruptHandler)handler_RS232,
(void *)0);
XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
XPAR_INTC_0_TMRCTR_0_VEC_ID,
(XInterruptHandler)handler_Timer,
(void *)0);
///////////////////////////////////////////////////////////////////////////////
//// мюярпнийю рюилепю //////////////////////////////////////////////////////
XTmrCtr_mSetLoadReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
0x61a8 //(25 MHz / 25000 = 1mS
//0x124F8//(75 MHz : 75.000 = 1 mS
);
XIntc_mEnableIntr(XPAR_INTC_0_BASEADDR,
// XPAR_XPS_TIMER_0_INTERRUPT_MASK |
XPAR_XPS_UARTLITE_0_INTERRUPT_MASK);
XTmrCtr_mSetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR,
0,
XTC_CSR_ENABLE_TMR_MASK |
XTC_CSR_ENABLE_INT_MASK |
XTC_CSR_AUTO_RELOAD_MASK |
XTC_CSR_DOWN_COUNT_MASK);
/////////////////////////////////////////////////////////////////////////////////
///////// мюярпнийю сярпниярб ббндю-бшбндю ////////////////////////////////////
XGpio_Initialize(&photo, XPAR_XPS_GPIO_0_DEVICE_ID);
XGpio_Initialize(&ircom, XPAR_XPS_GPIO_1_DEVICE_ID);
XGpio_Initialize(&kt, XPAR_XPS_GPIO_2_DEVICE_ID);
XGpio_SetDataDirection(&photo, 1, 0xffffffff); // ББНД
XGpio_SetDataDirection(&photo, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 1, 0x00); // БШБНД
XGpio_SetDataDirection(&ircom, 2, 0x00); // БШБНД
XGpio_SetDataDirection(&kt, 1, 0x00); // БШБНД
};
