//gpio_InstancePtr,dma_InstancePtr void test_fir(XGpio* gpio_InstancePtr, XAxiDma* dma_InstancePtr) { u32 output_samples_hardware[256]; u32 i; u8 rst_en = 1; u8 rst_disable = 0; u8 clk_en = 1; u8 clk_disable = 0; u8 output[NUMBER_OF_INSTANCES][NUMBER_OF_TLUTS_PER_INSTANCE][LUT_CONFIG_WIDTH]; LUT_config_type lut_configs[NUMBER_OF_INSTANCES*NUMBER_OF_TLUTS_PER_INSTANCE]; u32 group_sizes[NUMBER_OF_INSTANCES*NUMBER_OF_TLUTS_PER_INSTANCE+1] ={}; u8 parameter[NUMBER_OF_PARAMETERS]; u8 cdata1[] = {11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, 11,11,11,11,11,11}; u8 cdata3[] = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32}; u8 input_samples[] = {240,15,240,15,240,15,240,240,15,240,15,240,15,240,240,15,240,15,240,15,240,240,15,240,15,240,15,240,240,15,240}; void Start_Timer() { XTmrCtr_SetLoadReg(XPAR_AXI_TIMER_0_BASEADDR,XPAR_AXI_TIMER_0_DEVICE_ID,0); XTmrCtr_SetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR,XPAR_AXI_TIMER_0_DEVICE_ID,XTC_CSR_LOAD_MASK); XTmrCtr_SetControlStatusReg(XPAR_AXI_TIMER_0_BASEADDR,XPAR_AXI_TIMER_0_DEVICE_ID,0x00); XTmrCtr_Enable(XPAR_AXI_TIMER_0_BASEADDR,XPAR_AXI_TIMER_0_DEVICE_ID); }
void platform_setup_timer() { /* set the number of cycles the timer counts before interrupting */ /* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */ XTmrCtr_SetLoadReg(PLATFORM_TIMER_BASEADDR, 0, TIMER_TLR); /* reset the timers, and clear interrupts */ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* start the timers */ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); #if XPAR_INTC_0_HAS_FAST == 1 XIntc_RegisterFastHandler(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_INTR, (XFastInterruptHandler)xadapter_fasttimer_handler); #else /* Register Timer handler */ XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_INTR, (XInterruptHandler)xadapter_timer_handler, 0); #endif XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_MASK); }
void xadapter_fasttimer_handler(void) { timer_callback(); /* Load timer, clear interrupt bit */ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); }
/**************************** Counter *******************************************/ void counter_initialize(){ //TIMER RESET CODE //Turn off the timer XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, 0); //Put a zero in the load register XTmrCtr_SetLoadReg(XPAR_TMRCTR_0_BASEADDR, 1, 0); //Copy the load resister into the counter register XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, XTC_CSR_LOAD_MASK); //Enable (start) the timer XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, XTC_CSR_ENABLE_TMR_MASK); //END TIMER RESET CODE }
int opb_timer_init( void ) { // set the number of cycles the timer counts before interrupting XTmrCtr_SetLoadReg(PROFILE_TIMER_BASEADDR, 0, timer_clk_ticks); // reset the timers, and clear interrupts XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); // start the timers XTmrCtr_SetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); return 0; }
void xadapter_timer_handler(void *p) { //unsigned *timer_base = (unsigned *)PLATFORM_TIMER_BASEADDR; //unsigned tcsr = 0; timer_callback(); /* Load timer, clear interrupt bit */ XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); XTmrCtr_SetControlStatusReg(PLATFORM_TIMER_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); XIntc_AckIntr(XPAR_INTC_0_BASEADDR, PLATFORM_TIMER_INTERRUPT_MASK); }
void display_timer_handler(void *p) { timer_display_proc = 1; /* Load timer, clear interrupt bit */ XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK); XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); XIntc_AckIntr(XPAR_INTC_0_BASEADDR, TIMER1_INTERRUPT_MASK); }
/* This is an application defined callback function used to clear whichever interrupt was installed by the the vApplicationSetupTimerInterrupt() callback function - in this case the interrupt generated by the AXI timer. It is provided as an application callback because the kernel will run on lots of different MicroBlaze and FPGA configurations - not all of which will have the same timer peripherals defined or available. This example uses the AXI Timer 0. If that is available on your hardware platform then this example callback implementation should not require modification provided the example definition of vApplicationSetupTimerInterrupt() is also not modified. */ void vApplicationClearTimerInterrupt( void ) { unsigned long ulCSR; /* Clear the timer interrupt */ ulCSR = XTmrCtr_GetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0 ); XTmrCtr_SetControlStatusReg( XPAR_AXI_TIMER_0_BASEADDR, 0, ulCSR ); }
void init_network_timer_int() { /* set the number of cycles the timer counts before interrupting */ /* 100 Mhz clock => .01us for 1 clk tick. For 100ms, 10000000 clk ticks need to elapse */ XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_0_BASEADDR, 0, TIMER_TLR); /* reset the timers, and clear interrupts */ XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* start the timers */ XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); /* Register Timer handler */ XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR, (XInterruptHandler)network_timer_handler, 0); }
int main() { int numClockCycles = 0; Xil_ICacheEnable(); Xil_DCacheEnable(); print("---Entering main---\n\r"); print("---Trial Name \t Trial # \t Clock Cycles---\n\r"); int i = 0; // Extra Method contains an interrupt routine which is set to go off at timed intervals extra_method(); for( i=0; i < NUMBER_OF_TRIALS; i++) { //TIMER RESET CODE //Turn off the timer XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, 0); //Put a zero in the load register XTmrCtr_SetLoadReg(XPAR_TMRCTR_0_BASEADDR, 1, 0); //Copy the load register into the counter register XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, XTC_CSR_LOAD_MASK); //Enable (start) the timer XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, XTC_CSR_ENABLE_TMR_MASK); //END TIMER RESET CODE //blinkLED(int numberOfBlinks); //offLED(); //onLED(); //sevenSegment(); //printLongerStrings(); // Write this function //printShortStrings(); // Write this function //printfShortStrings(); // Write this function //xil_printfShortStrings(); // Write this function //intAddAndMultiply(); // Write this function //floatAddAndMultiply(); // Write this function numClockCycles = XTmrCtr_GetTimerCounterReg(XPAR_TMRCTR_0_BASEADDR, 1); xil_printf("print \t%d\t%d\n", i,numClockCycles ); } return 0; }
void init_display_timer_int() { // Set timer speed XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_1_BASEADDR, 0, TIMER_DISPLAY_TLR); /* reset the timers, and clear interrupts */ XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); /* start the timers */ XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_1_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); /* Register Timer handler */ XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR, XPAR_XPS_INTC_0_XPS_TIMER_1_INTERRUPT_INTR, (XInterruptHandler)display_timer_handler, 0); timer_display_proc = 0; }
void timer_int_handler(void * baseaddr_p) { unsigned int csr; int num; unsigned int MskAnodes; csr = XTmrCtr_GetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0); if (csr & XTC_CSR_INT_OCCURED_MASK && win_flag==0) { count++; if (count%2==0) { MskAnodes=0x00000D00; num=(TIME_LIMIT-time0)/10; } else { MskAnodes=0x00000E00; num=(TIME_LIMIT-time0)%10; } ssBuf = MskAnodes | rgfsNumMap[num]; Xil_Out32(XPAR_SEVSEG_DISP_12BITS_BASEADDR, ssBuf); } if (count==200) { count=0; time0++; DrawBack(3,1119,EMPTY); DrawTime(88, EMPTY); if (time0>20) DrawTime(TIME_LIMIT-time0, CURSOR); else DrawTime(TIME_LIMIT-time0, turn); } if (time0>TIME_LIMIT) { time0=0; if (turn==HUMAN_PLAYER) { turn=COMPUTER_PLAYER; xil_printf("\r\nComputer Player's turn!\r\n"); } else { turn=HUMAN_PLAYER; xil_printf("\r\nHuman Player's turn!\r\n"); } } XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, csr); }
int main (void) { XGpio dip; int dip_check; static XPs2 Ps2Inst; XPs2_Config *ConfigPtr; u32 StatusReg; u32 BytesReceived; u8 RxBuffer; int key_count=0; int i; status=PVP; int x_cur=7, y_cur=7, x_pos=0, y_pos=0; XGpio_Initialize(&dip, XPAR_DIP_SWITCHES_8BITS_DEVICE_ID); XGpio_SetDataDirection(&dip, 1, 0xffffffff); ConfigPtr = XPs2_LookupConfig(XPAR_XPS_PS2_0_0_DEVICE_ID); XPs2_CfgInitialize(&Ps2Inst, ConfigPtr, ConfigPtr->BaseAddress); XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR, (XInterruptHandler) timer_int_handler, (void *)XPAR_XPS_TIMER_0_BASEADDR); XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR); XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR, 0x1); XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_0_BASEADDR, 0, 333333); XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK ); XIntc_EnableIntr(XPAR_XPS_TIMER_0_BASEADDR, XPAR_XPS_TIMER_0_INTERRUPT_MASK); XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK); microblaze_enable_interrupts(); InitializeGame(x_cur, y_cur);status=PVP; xil_printf("-- Game Starts! --\r\n"); xil_printf("\r\nHuman Player's turn!\r\n"); int vga_input; vga_input=(0<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(1<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(2<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(3<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(4<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(5<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(6<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(7<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(8<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(0<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(0<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(1<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(2<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(3<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(4<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(5<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(6<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(7<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(8<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(0<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(1<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(2<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(3<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(4<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(5<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(6<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(7<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(8<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(0<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(1<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(2<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(3<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(4<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(5<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(6<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(7<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(8<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(1<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(2<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(3<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(4<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(5<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(6<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(7<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(8<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(9<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(10<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(11<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(12<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(13<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(14<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(15<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(16<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(17<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(18<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(19<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(20<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(21<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(22<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(23<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(24<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(25<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(26<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(27<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(28<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(29<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); vga_input=(9<<24)+(30<<16)+(1<<8)+3; VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input); while (1) { if (turn==HUMAN_PLAYER || (turn==COMPUTER_PLAYER && status==PVP)) { do { if (turn==COMPUTER_PLAYER && status==PVC) break; dip_check=XGpio_DiscreteRead(&dip, 1); StatusReg = XPs2_GetStatus(&Ps2Inst); }while((StatusReg & XPS2_STATUS_RX_FULL) == 0); BytesReceived = XPs2_Recv(&Ps2Inst, &RxBuffer, 1); key_count=(key_count+1)%3; if (key_count==0) { if (RxBuffer==0x21&& win_flag==0) { DrawNumber(level,3,2,EMPTY); if(level==1) level=2; else level=1; if(status==PVC ) DrawNumber(level,3,2,0); else if(status==CVP) DrawNumber(level,3,2,1); else DrawNumber(level,3,2,EMPTY); } if (RxBuffer==0x1D && win_flag==0) { EraseCursor(x_cur, y_cur); if (y_cur<=0) y_cur=14; else y_cur--; DrawChess(x_cur, y_cur, CURSOR); } if (RxBuffer==0x1B && win_flag==0) { EraseCursor(x_cur, y_cur); if (y_cur>=14) y_cur=0; else y_cur++; DrawChess(x_cur, y_cur, CURSOR); } if (RxBuffer==0x1C && win_flag==0) { EraseCursor(x_cur, y_cur); if (x_cur<=0) x_cur=14; else x_cur--; DrawChess(x_cur, y_cur, CURSOR); } if (RxBuffer==0x23 && win_flag==0) { EraseCursor(x_cur, y_cur); if (x_cur>=14) x_cur=0; else x_cur++; DrawChess(x_cur, y_cur, CURSOR); } if (RxBuffer==0x5A && win_flag==0) { DrawBack(3,1119,EMPTY); if (board_state[x_cur][y_cur]==EMPTY) { if(status==CVP) DrawChess(x_cur, y_cur, 1-turn); else DrawChess(x_cur, y_cur, turn); board_state[x_cur][y_cur]=turn; board_record[BackTimes].x=x_cur; board_record[BackTimes].y=y_cur; BackTimes++; count=0; time0=0; if (turn==COMPUTER_PLAYER) step_flag=1; if (CheckWin(x_cur,y_cur,turn)==1) { xil_printf("\r\nHuman Player wins!\r\n"); win_flag=1; DrawWinning(0, 1, EMPTY); if(status==CVP) DrawWinning(0, 1, 1-turn); else DrawWinning(0, 1, turn); } if (CheckBan(x_cur,y_cur,turn)==1){ xil_printf("\r\nComputer Player wins!\r\n"); win_flag=1; DrawWinning(0, 1, EMPTY); if(status==CVP) DrawWinning(0, 1, turn); else DrawWinning(0, 1, 1-turn); } else { if (turn==HUMAN_PLAYER) turn=COMPUTER_PLAYER; else turn=HUMAN_PLAYER; xil_printf("\r\nComputer Player's turn!\r\n"); } } } if (RxBuffer==0x29 && turn==HUMAN_PLAYER && win_flag==0) { count=0;time0=0; if (status==PVP) { x_cur=7; y_cur=7; for (i=0; i<256; i++) { board_record[i].x=0; board_record[i].y=0; } InitializeGame(x_cur, y_cur);status=PVP; DrawStatus(1, 21, EMPTY,status); status=PVC; DrawNumber(level,3,2,0); DrawStatus(1, 21, COMPUTER_PLAYER,status); } else if(status==PVC) { x_cur=7; y_cur=7; for (i=0; i<256; i++) { board_record[i].x=0; board_record[i].y=0; } InitializeGame(x_cur, y_cur);status=PVP; DrawStatus(1, 21, EMPTY,status); status=CVP; DrawNumber(level,3,2,1); DrawStatus(1, 21, COMPUTER_PLAYER,status); turn=COMPUTER_PLAYER; } else if(status==CVP) { x_cur=7; y_cur=7; for (i=0; i<256; i++) { board_record[i].x=0; board_record[i].y=0; } InitializeGame(x_cur, y_cur);status=PVP; DrawStatus(1, 21, EMPTY,status); status=PVP; DrawStatus(1, 21, COMPUTER_PLAYER,status); } } if (RxBuffer==0x76) { x_cur=7; y_cur=7; for (i=0; i<256; i++) { board_record[i].x=0; board_record[i].y=0; } InitializeGame(x_cur, y_cur);status=PVP; } if (RxBuffer==0x2D) { if(BackTimes>0){ BackTimes--; x_cur=board_record[BackTimes].x; y_cur=board_record[BackTimes].y; board_state[x_cur][y_cur]=EMPTY; DrawChess(x_cur,y_cur,EMPTY); turn=1-turn; if(status==PVC) { BackTimes--; x_cur=board_record[BackTimes].x; y_cur=board_record[BackTimes].y; board_state[x_cur][y_cur]=EMPTY; DrawChess(x_cur,y_cur,EMPTY); turn=HUMAN_PLAYER; } DrawBack(3,1119,turn); } } } } if (turn==COMPUTER_PLAYER && (status==PVC ||status==CVP )&& win_flag==0) { if (step_flag==0) { if (x_cur-1<0) x_pos=x_cur+1; else x_pos=x_cur-1; y_pos=y_cur; step_flag=1; } else { if(level==2||level==3){ EvaluateComputerMove(board_state, 0, MIN_INFINITY, MAX_INFINITY, 0, 0); x_pos=maxMoveX; y_pos=maxMoveY; xil_printf("\r\n computer \r\n");} else { everyScore(Computer); current_pos=best(Computer); x_pos=current_pos.y; y_pos=current_pos.x; xil_printf("\r\n computer \r\n"); } } xil_printf("\r\n%x, %x\r\n", x_pos, y_pos); if(status==CVP) DrawChess(x_pos, y_pos, 1-turn); else DrawChess(x_pos, y_pos, turn); board_state[x_pos][y_pos]=COMPUTER_PLAYER; board_record[BackTimes].x=x_pos; board_record[BackTimes].y=y_pos; BackTimes++; count=0; time0=0; if (CheckWin(x_pos, y_pos, turn)) { xil_printf("\r\nComputer Player wins!\r\n"); win_flag=1; DrawWinning(0,1, EMPTY); if(status==CVP) DrawWinning(0,1, 1-turn); else DrawWinning(0,1, turn); turn=HUMAN_PLAYER; } else { turn=HUMAN_PLAYER; xil_printf("\r\nHuman Player's turn!\r\n"); } } } return 0; }