Exemplo n.º 1
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return Returns 0.
*******************************************************************************/
int main()
{
	UINT32 StartCount;

	MajorRev     = 1;
	MinorRev     = 1;
	RcRev        = 1;
	DriverEnable = TRUE;
	LastEnable   = FALSE;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

#ifdef XPAR_AXI_IIC_0_BASEADDR
	HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);
#else
	HAL_PlatformInit(XPAR_AXI_IIC_MAIN_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);
#endif

	Xil_ExceptionEnable();

	SetVideoResolution(RESOLUTION_640x480);
	InitHdmiAudioPcore();

	APP_PrintRevisions();       /* Display S/W and H/W revisions */

	DBG_MSG("To change the video resolution press:\r\n");
	DBG_MSG("  '0' - 640x480;  '1' - 800x600;  '2' - 1024x768; '3' - 1280x720 \r\n");
	DBG_MSG("  '4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.\r\n");

	ADIAPI_TransmitterInit();   /* Initialize ADI repeater software and h/w */

	ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);

	StartCount = HAL_GetCurrentMsCount();

	while(1)
	{
		if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
		{
			StartCount = HAL_GetCurrentMsCount();
			if (APP_DriverEnabled())
			{
				ADIAPI_TransmitterMain();
			}
		}
		APP_ChangeResolution();
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return(0);
}
Exemplo n.º 2
0
/******************************************************************************
* @brief Main function.
*
* @return Always returns 0.
******************************************************************************/
int main() 
{

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   I2C_Init_axi(IIC_BASEADDR, AD7991IICAddr);

   unsigned char rxBuffer[2] = {0x00, 0x00};

   // Configure AD7991
   /*
    	Use external reference (2V, selected from Jumper JP1)
    	Read all 3 Channels
    	4th Channel used as reference
    */
   AD7991_Config(0,1,1,1,1,0,0,0);

	   // Print the value read on one of the channels
	   AD7991_Print(20,VREF);

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}
Exemplo n.º 3
0
int main(void)
{
	Xil_ICacheEnable();
	Xil_DCacheEnable();
	DemoInitialize();
	DemoRun();
	return 0;
}
Exemplo n.º 4
0
/***************************************************************************//**
 * @brief main
*******************************************************************************/
int main(void)
{
	Xil_ICacheEnable();
	Xil_DCacheEnable();

	gpio_init(GPIO_DEVICE_ID);
	gpio_direction(54 + 46, 1);
	spi_init(SPI_DEVICE_ID, 1, 0);

	adc_init();
	dac_init(DATA_SEL_DDS);

	ad9361_phy = ad9361_init(&default_init_param);

	ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
	ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);

#ifdef DAC_DMA
	dac_init(DATA_SEL_DMA);
#else
	dac_init(DATA_SEL_DDS);
#endif

#ifdef CAPTURE_SCRIPT
	adc_capture(16384, ADC_DDR_BASEADDR);
	while(1);
#endif
	get_help(NULL, 0);

	while(1)
	{
		console_get_command(received_cmd);
		invalid_cmd = 0;
		for(cmd = 0; cmd < cmd_no; cmd++)
		{
			param_no = 0;
			cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
											  param, &param_no);
			if(cmd_type == UNKNOWN_CMD)
			{
				invalid_cmd++;
			}
			else
			{
				cmd_list[cmd].function(param, param_no);
			}
		}
		if(invalid_cmd == cmd_no)
		{
			console_print("Invalid command!\n");
		}
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Exemplo n.º 5
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return Returns 0.
*******************************************************************************/
int main()
{
	UINT32 StartCount;

	MajorRev     = 1;
	MinorRev     = 1;
	RcRev        = 1;
	DriverEnable = TRUE;
	LastEnable   = FALSE;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR,	/* Perform any required platform init */
					 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
					 XPAR_SCUGIC_SINGLE_DEVICE_ID,
					 XPAR_SCUTIMER_INTR);

	Xil_ExceptionEnable();

	/* Set the default values for 1080P 60Hz */
	CLKGEN_SetRate(148500000, 200000000);
	InitHdmiVideoPcore(1920,
					   1080,
					   280,
					   45,
					   44,
					   5,
					   88,
					   4);
	InitHdmiAudioPcore();

	APP_PrintRevisions();       /* Display S/W and H/W revisions */

	ADIAPI_TransmitterInit();   /* Initialize ADI repeater software and h/w */

	ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);

	StartCount = HAL_GetCurrentMsCount();

	while(1)
	{
		if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
		{
			StartCount = HAL_GetCurrentMsCount();
			if (APP_DriverEnabled())
			{
				ADIAPI_TransmitterMain();
			}
		}
	}

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return(0);
}
Exemplo n.º 6
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return 0.
*******************************************************************************/
int main(){

    uint32_t mode;

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    /* AD9467 Setup. */
    ad9467_setup(SPI_DEVICE_ID, 0);

    /* AD9517 Setup. */
    ad9517_setup(SPI_DEVICE_ID, 1);    // Initialize device.
    ad9517_power_mode(3, 0);                     // Set channel 3 for normal operation
    ad9517_frequency(3, 250000000);              // Set the channel 3 frequency to 250Mhz
    ad9517_update();                             // Update registers

    /* Read the device ID for AD9467 and AD9517. */
    xil_printf("\n\r********************************************************************\r\n");
    xil_printf("  ADI AD9467-FMC-EBZ Reference Design\n\r");
    xil_printf("  AD9467 CHIP ID: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_ID));
    xil_printf("  AD9467 CHIP GRADE: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE));
    xil_printf("  AD9517 CHIP ID: 0x%02x", ad9517_read(AD9517_REG_PART_ID));
    xil_printf("\n\r********************************************************************\r\n");

    /* AD9467 test. */
    adc_setup(0);

    for (mode = MIDSCALE; mode <= ONE_ZERO_TOGGLE; mode++)        // Data pattern checks
    {
        adc_test(mode, OFFSET_BINARY);       // Data format is offset binary
        adc_test(mode, TWOS_COMPLEMENT);     // Data format is twos complement
    }
    xil_printf("Testing done.\n\r");
    /* AD9467 Setup for data acquisition */
    ad9467_output_invert(0);    // Output invert Off
    ad9467_transfer();          // Synchronously update registers
    ad9467_output_format(0);    // Offset binary
    ad9467_transfer();          // Synchronously update registers
    ad9467_reset_PN9(0);        // Clear PN9 bit
    ad9467_transfer();          // Synchronously update registers
    ad9467_reset_PN23(0);       // Clear PN23 bit
    ad9467_transfer();          // Synchronously update registers
    ad9467_test_mode(0);        // Test mode Off
    ad9467_transfer();          // Synchronously update registers

    xil_printf("Start capturing data...\n\r");

    while(1)
    {
        adc_capture(1024, DDR_BASEADDR);
    }

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
Exemplo n.º 7
0
int main(void)
{
	microblaze_disable_interrupts();

	#if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
	{
		Xil_ICacheInvalidate();
		Xil_ICacheEnable();
	}
	#endif

	#if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
	{
		Xil_DCacheInvalidate();
		Xil_DCacheEnable();
	}
	#endif

	// Before a queue is used it must be explicitly created. The queue is
	// created to hold a maximum of 5 character pointers.
	xPrintQueue = xQueueCreate(5, sizeof(char*));

	// The tasks are going to use a pseudo random delay, seed the random number
	// generator.
	srand(567);

	// Check the queue was created successfully.
	if (xPrintQueue != NULL)
	{
		// Create two instances of the tasks that send messages to the gatekeeper.
		// The index to the string the task uses is passed to the task via the
		// task parameter (the 4th parameter to xTaskCreate()). The tasks are
		// created at different priorities so the higher priority task will
		// occasionally preempt the lower priority task.
		xTaskCreate(prvPrintTask, "Print1", configMINIMAL_STACK_SIZE, (void*)0,
			tskIDLE_PRIORITY+1, NULL);
		xTaskCreate(prvPrintTask, "Print2", configMINIMAL_STACK_SIZE, (void*)1,
			tskIDLE_PRIORITY+2, NULL);

		// Create the gatekeeper task. This is the only task that is permitted
		// to directly access standard out.
		xTaskCreate(prvStdioGatekeeperTask, "Gatekeeper", configMINIMAL_STACK_SIZE,
			NULL, tskIDLE_PRIORITY, NULL);

		// Start the scheduler so the created tasks start executing.
		vTaskStartScheduler();
	}

	// If all is well then main() will never reach here as the scheduler will
	// now be running the tasks. If main() does reach here then it is likely
	// that there was insufficient heap memory available for the idle task
	// to be created. Chapter 5 provides more information on memory management.
	for (;;);

	return 0;
}
Exemplo n.º 8
0
void
enable_caches()
{
#ifdef XPAR_MICROBLAZE_USE_ICACHE
    Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE
    Xil_DCacheEnable();
#endif
}
Exemplo n.º 9
0
int main(void)
{
    microblaze_disable_interrupts();

    #if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
    {
        Xil_ICacheInvalidate();
        Xil_ICacheEnable();
    }
    #endif

    #if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
    {
        Xil_DCacheInvalidate();
        Xil_DCacheEnable();
    }
    #endif

	// The queue is created to hold a maximum of 3 structures of type xData.
	xQueue = xQueueCreate(3, sizeof(xData));

	if (xQueue != NULL)
	{
		// Create two instances of the task that will write to the queue. The
		// parameter is used to pass the structure that the task will write to
		// the queue, so one task will continuously send xStructsToSend[0] to
		// the queue while the other task will continuously send xStructsSend[1].
		// Both tasks are created at priority 2 which is above the priority of
		// the receiver.
		xTaskCreate(vSenderTask, "Sender1", configMINIMAL_STACK_SIZE,
			(void*)&xStructsToSend[0], tskIDLE_PRIORITY+2, NULL);
		xTaskCreate(vSenderTask, "Sender2", configMINIMAL_STACK_SIZE,
			(void*)&xStructsToSend[1], tskIDLE_PRIORITY+2, NULL);

		// Create the task that will read from the queue. The task is created
		// with priority 1, so below the priority of the sender tasks.
		xTaskCreate(vReceiverTask, "Receiver", configMINIMAL_STACK_SIZE,
			NULL, tskIDLE_PRIORITY+1, NULL);

		// Start the scheduler so the created tasks start executing.
		vTaskStartScheduler();
	}
	else
	{
		// The queue could not be created.
	}

	// If all is well then main() will never reach here as the scheduler will
	// now be running the tasks. If main() does reach here then it is likely
	// that there was insufficient heap memory available for the idle task to
	// be created. Chapter 5 provides more information on memory management.
	for (;;);

	return 0;
}
Exemplo n.º 10
0
Arquivo: main.c Projeto: PyHDI/PyCoRAM
//------------------------------------------------------------------------------
int main() 
{
  Xil_ICacheEnable();
  Xil_DCacheEnable();

  while(1){ main_loop(); }

  Xil_DCacheDisable();
  Xil_ICacheDisable();
  return 0;
}
Exemplo n.º 11
0
/***	main()
**
**	Parameters:
**		none
**
**	Return Value:
**		none
**
**	Errors:
**		none
**
**	Description:
**		Handles opening caches and wraps demo function calls.
*/
int main()
{
    Xil_ICacheEnable();
    Xil_DCacheEnable();

    DemoInitialize();
    DemoRun();
    DemoCleanup();

    return 0;
}
Exemplo n.º 12
0
int main(void)
{
	Xil_ICacheEnable();
	Xil_DCacheEnable();

	DemoInitialize();
	DemoRun();

	cleanup_platform();

	return 0;
}
int main (void) {


   /*
    * Enable and initialize cache
    */
   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheInvalidate();
      Xil_ICacheEnable();
   #endif

   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheInvalidate();
       Xil_DCacheEnable();
   #endif

   print("-- Entering main() --\r\n");

   /* 
    * MemoryTest routine will not be run for the memory at 
    * 0x84c00000 (FLASH_2Mx16)
    * because it is a read-only memory
    */


   /* 
    * MemoryTest routine will not be run for the memory at 
    * 0x00000000 (dlmb_cntlr)
    * because it is being used to hold a part of this application program
    */

   /*
    * Disable cache and reinitialize it so that other
    * applications can be run with no problems
    */
   #if XPAR_MICROBLAZE_0_USE_DCACHE
      Xil_DCacheDisable();
      Xil_DCacheInvalidate();
   #endif

   #if XPAR_MICROBLAZE_0_USE_ICACHE
      Xil_ICacheDisable();
      Xil_ICacheInvalidate();
   #endif


   print("-- Exiting main() --\r\n");
   return 0;
}
Exemplo n.º 14
0
int main() 
{
   static XIntc intc;
   Xil_ICacheEnable();
   Xil_DCacheEnable();
   print("---Entering main---\n\r");
   

   //XIntc_DeviceInterruptHandler(XPAR_INTC_0_DEVICE_ID);
   //print (XPAR_INTC_0_DEVICE_ID);


   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for axi_intc_0...\r\n");
      
      status = IntcSelfTestExample(XPAR_AXI_INTC_0_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_AXI_INTC_0_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }
   
   /*
    * Peripheral SelfTest will not be run for axi_uartlite_0
    * because it has been selected as the STDOUT device
    */

   print("---Exiting main---\n\r");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
Exemplo n.º 15
0
void
enable_caches()
{
#ifdef __PPC__
    Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
    Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
#elif __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_ICACHE 
    Xil_ICacheEnable();
#endif
#ifdef XPAR_MICROBLAZE_USE_DCACHE 
    Xil_DCacheEnable();
#endif
#endif
}
int main(void)
{
	int Status;

#ifdef XPAR_XUARTNS550_NUM_INSTANCES
	XUartNs550_SetBaud(STDIN_BASEADDRESS, XPAR_XUARTNS550_CLOCK_HZ, 9600);
	XUartNs550_SetLineControlReg(STDIN_BASEADDRESS, XUN_LCR_8_DATA_BITS);
#endif

#if XPAR_MICROBLAZE_USE_ICACHE
	Xil_ICacheInvalidate();
	Xil_ICacheEnable();
#endif

#if XPAR_MICROBLAZE_USE_DCACHE
	Xil_DCacheInvalidate();
	Xil_DCacheEnable();
#endif

	AxiEthernetUtilErrorTrap("\r\n--- Enter main() ---");
	AxiEthernetUtilErrorTrap("This test may take several minutes to finish");

	/*
	 * Call the Axi Ethernet vlan example main function
	 */
	Status = AxiEthernetExtVlanExample(&IntcInstance,
						&AxiEthernetInstance,
						&DmaInstance,
						AXIETHERNET_DEVICE_ID,
						AXIDMA_DEVICE_ID,
						AXIETHERNET_IRPT_INTR,
						DMA_RX_IRPT_INTR,
						DMA_TX_IRPT_INTR);
	if (Status != XST_SUCCESS) {
		AxiEthernetUtilErrorTrap("Failed test intr sgdma");
		AxiEthernetUtilErrorTrap("--- Exiting main() ---");
		return XST_FAILURE;
	}

	AxiEthernetUtilErrorTrap("Test passed");
	AxiEthernetUtilErrorTrap("--- Exiting main() ---");

	return XST_SUCCESS;

}
Exemplo n.º 17
0
/***************************************************************************//**
 * @brief Main function.
 *
 * @return 0.
*******************************************************************************/
int main(){

	u32 mode;

	Xil_ICacheEnable();
    Xil_DCacheEnable();

    /* AD9467 Setup. */
    ad9467_setup(XPAR_AXI_SPI_0_BASEADDR, 1);

	/* AD9517 Setup. */
	ad9517_setup(XPAR_AXI_SPI_0_BASEADDR, 2);	// Initialize device.
	ad9517_power_mode(3, 0);					// Set channel 3 for normal operation
	ad9517_frequency(3, 250000000); 			// Set the channel 3 frequency to 250Mhz
	ad9517_update();							// Update registers

	/* Read the device ID for AD9467 and AD9517. */
	xil_printf("AD9467[REG_CHIP_ID]: %02x\n\r",
			   ad9467_read(AD9467_REG_CHIP_ID));
	xil_printf("AD9467[REG_CHIP_GRADE]: %02x\n\r",
			    ad9467_read(AD9467_REG_CHIP_GRADE));
	xil_printf("AD9517[REG_PART_ID]: %02x\n\r",
			    ad9517_read(AD9517_REG_PART_ID));

	/* AD9467 test. */
	adc_setup(0);
	for (mode = 0x01; mode <= 0x07; mode++)		// Data pattern checks
	{
		adc_test(mode, 0x0);    // Data format is offset binary
		adc_test(mode, 0x1);    // Data format is twos complement
	}
	ad9467_output_invert(0);    // Output invert Off
	ad9467_output_format(0);    // Offset binary
	ad9467_reset_PN9(0);        // Clear PN9 bit
	ad9467_reset_PN23(0);       // Clear PN23 bit
	ad9467_test_mode(0);        // Test mode Off
	ad9467_transfer();          // Synchronously update registers

	xil_printf("done\n\r");

	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Exemplo n.º 18
0
void SCREEN_Init(UINT32 resolution)
{

	UINT32 StartCount;

		MajorRev     = 1;
		MinorRev     = 1;
		RcRev        = 1;
		DriverEnable = TRUE;
		LastEnable   = FALSE;

		Xil_ICacheEnable();
		Xil_DCacheEnable();

	#ifdef XPAR_AXI_IIC_0_BASEADDR
		HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR,	/* Perform any required platform init */
						 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
						 XPAR_SCUGIC_SINGLE_DEVICE_ID,
						 XPAR_SCUTIMER_INTR);
	#else
		HAL_PlatformInit(XPAR_AXI_IIC_MAIN_BASEADDR,	/* Perform any required platform init */
						 XPAR_SCUTIMER_DEVICE_ID,	/* including hardware reset to HDMI devices */
						 XPAR_SCUGIC_SINGLE_DEVICE_ID,
						 XPAR_SCUTIMER_INTR);
	#endif

		Xil_ExceptionEnable();

		SetVideoResolution( resolution);
		InitHdmiAudioPcore();

		APP_PrintRevisions();       /* Display S/W and H/W revisions */

//		DBG_MSG("To change the video resolution press:\r\n");
//		DBG_MSG("  '0' - 640x480;  '1' - 800x600;  '2' - 1024x768; '3' - 1280x720 \r\n");
//		DBG_MSG("  '4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.\r\n");

		ADIAPI_TransmitterInit();   /* Initialize ADI repeater software and h/w */

		ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);

		StartCount = HAL_GetCurrentMsCount();

}
Exemplo n.º 19
0
/**
* @brief    Disable MPU for Cortex R5 processors. This function invalidates I
*           cache and flush the D Caches, and then disabes the MPU.
*
* @param	None.
*
* @return	None.
*
******************************************************************************/
void Xil_DisableMPU(void)
{
	u32 CtrlReg, Reg;
	s32 DCacheStatus=0, ICacheStatus=0;
	/* enable caches only if they are disabled */

#if defined (__GNUC__)
	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
	mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
#endif
	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
		DCacheStatus=1;
	}
	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
		ICacheStatus=1;
	}

	if(DCacheStatus != 0) {
		Xil_DCacheDisable();
	}
	if(ICacheStatus != 0){
		Xil_ICacheDisable();
	}

	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
#if defined (__GNUC__)
	Reg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
	mfcp(XREG_CP15_SYS_CONTROL,Reg);
#endif
	Reg &= ~(0x00000001U);
	dsb();
	mtcp(XREG_CP15_SYS_CONTROL, Reg);
	isb();
	/* enable caches only if they are disabled in routine*/
	if(DCacheStatus != 0) {
		Xil_DCacheEnable();
	}
	if(ICacheStatus != 0) {
		Xil_ICacheEnable();
	}
}
Exemplo n.º 20
0
int main(void)
{
    microblaze_disable_interrupts();

    #if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
    {
        Xil_ICacheInvalidate();
        Xil_ICacheEnable();
    }
    #endif

    #if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
    {
        Xil_DCacheInvalidate();
        Xil_DCacheEnable();
    }
    #endif

	// Create the first task at priority 2. The task parameter is not used
	// and set to NULL. The task handle is also not used so is also set to NULL.
	xTaskCreate(vTask1, "Task 1", configMINIMAL_STACK_SIZE, NULL, 
							tskIDLE_PRIORITY+2, NULL);
	// The task is created at priority 2-----^

	// Create the second task at priority 1 - which is lower than the priority
	// given to Task 1. Again the task parameter is not used so is set to NULL -
	// BUT this time the task handle is required so the address of xTask2Handle
	// is passed int the last parameter.
	xTaskCreate(vTask2, "Task 2", configMINIMAL_STACK_SIZE, NULL,
							tskIDLE_PRIORITY+1, &xTask2Handle);
	// The task handle is the last parameter ___^^^^^^^^^^^^^

	// Start the scheduler so the tasks start executing.
	vTaskStartScheduler();

	// If all is well the main() will never reach here as the scheduler will
	// now be running the tasks. If main() does reach here then it is likely
	// that there was insufficient heap memory available for the idle task to
	// be created. Chapter 5 provides more information on memory management.
	for (;;);

	return 0;
}
void XFsbl_EccInitialize(u32 Address, u32 Length)
{
	u32 Index=0U;

	/* Disable cache to ensure proper ECC initialization */
	Xil_DCacheDisable();
	while (Index<Length)
	{
		XFsbl_Out32(Address+Index, 1U) ;
		Index += 4U;
	}
	Xil_DCacheEnable();

	XFsbl_Printf(DEBUG_INFO,
	  "Address 0x%0lx, Length %0lx, ECC initialized \r\n",
		Address, Length);

	return ;
}
Exemplo n.º 22
0
void  BSP_Init (void)
{
    CPU_IntDis();                                               /* Disable all interrupts.                              */

    Xil_ICacheEnable();                                         /* Enable the instruction cache.                        */
    Xil_DCacheEnable();                                         /* Enable the Data cache.                               */

    CSP_IntInit();                                              /* Initialize Interrupt controller module.              */
#ifdef STDOUT_IS_PS7_UART
    XUartPs         Uart_Ps_0;                                  /* Use the PS UART for Zynq devices.                    */
    XUartPs_Config *Config_0;

    Config_0 = XUartPs_LookupConfig(UART_DEVICE_ID);
    XUartPs_CfgInitialize(&Uart_Ps_0, Config_0, Config_0->BaseAddress);
    XUartPs_SetBaudRate(&Uart_Ps_0, 115200);
#elif defined(STDOUT_IS_16550)
    XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
    XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
#endif
}
Exemplo n.º 23
0
int main() {
	int numClockCycles = 0;
	Xil_ICacheEnable();
	Xil_DCacheEnable();
	print("---Entering main---\n\r");
	print("---Trial Name \t Trial # \t Clock Cycles---\n\r");
	int i = 0;
	// Extra Method contains an interrupt routine which is set to go off at timed intervals
    extra_method();


    for( i=0; i < NUMBER_OF_TRIALS; i++) {
     	//TIMER RESET CODE
 		//Turn off the timer
 		XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, 0);
 		//Put a zero in the load register
 		XTmrCtr_SetLoadReg(XPAR_TMRCTR_0_BASEADDR, 1, 0);
 		//Copy the load register into the counter register
 		XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1, XTC_CSR_LOAD_MASK);
 		//Enable (start) the timer
 		XTmrCtr_SetControlStatusReg(XPAR_TMRCTR_0_BASEADDR, 1,	XTC_CSR_ENABLE_TMR_MASK);
 		//END TIMER RESET CODE

 		//blinkLED(int numberOfBlinks);
		//offLED();
		//onLED();
		//sevenSegment();
		//printLongerStrings(); // Write this function
		//printShortStrings(); // Write this function
		//printfShortStrings(); // Write this function
		//xil_printfShortStrings(); // Write this function
		//intAddAndMultiply(); // Write this function
		//floatAddAndMultiply(); // Write this function


 		numClockCycles = XTmrCtr_GetTimerCounterReg(XPAR_TMRCTR_0_BASEADDR, 1);
 		xil_printf("print  \t%d\t%d\n", i,numClockCycles );

    }
    return 0;
}
Exemplo n.º 24
0
int main( void )
{
    microblaze_disable_interrupts();

    #if defined( XPAR_MICROBLAZE_USE_ICACHE ) && ( XPAR_MICROBLAZE_USE_ICACHE != 0 )
    {
        Xil_ICacheInvalidate();
        Xil_ICacheEnable();
    }
    #endif

    #if defined( XPAR_MICROBLAZE_USE_DCACHE ) && ( XPAR_MICROBLAZE_USE_DCACHE != 0 )
    {
        Xil_DCacheInvalidate();
        Xil_DCacheEnable();
    }
    #endif

	// Start the two tasks
	xTaskCreate(prvHelloWorld, "HW", configMINIMAL_STACK_SIZE, NULL,
				mainHELLO_WORLD_TASK_PRIORITY, NULL);
	xTaskCreate(prvGoodBye, "GB", configMINIMAL_STACK_SIZE, NULL,
				mainGOOD_BYE_TASK_PRIORITY, NULL);

	// Start the tasks and timer running
	vTaskStartScheduler();

	// If all is well, the scheduler will now be running, and the following line
	// will never be reached. If the following line does execute, then there was
	// insufficient FreeRTOS heap memory available for the idle and/or timer
	// tasks to be created. See the memory management section on the FreeRTOS
	// web site for more details.
	for (;;);
	
	return 0;
}
Exemplo n.º 25
0
int main(void)
{
	XIntc intc;
	XTmrCtr tmrctr;
	int Status;

	Xil_ICacheEnable();
	Xil_DCacheEnable();

	// Initialize the timer counter so that it's ready to use,
	// specify the device ID that is generated in xparameters.h
	Status = XTmrCtr_Initialize(&tmrctr, XPAR_TMRCTR_0_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Initialize the interrupt controller driver so that 
	// it's ready to use, specify the device ID that is generated in
	// xparameters.h
	Status = XIntc_Initialize(&intc, XPAR_INTC_0_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Connect a device driver handler that will be called when an interrupt
	// for the device occurs, the device driver handler performs the specific
	// interrupt processing for the device
	Status = XIntc_Connect(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID, 
			XTmrCtr_InterruptHandler, &tmrctr);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Enable the interrupt for the timer counter
	XIntc_Enable(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID );

	// Start the interrupt controller such that interrupts are enabled for
	// all devices that cause interrupts, specific real mode so that
	// the timer counter can cause interrupts thru the interrupt controller.
	Status = XIntc_Start(&intc, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	// Initialize the exception table.
	Xil_ExceptionInit();

	// Register the interrupt controller handler with the exception table.
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
    	(Xil_ExceptionHandler)XIntc_InterruptHandler, &intc);

	// Enable non-critical exceptions.
	Xil_ExceptionEnable();

	// Setup the handler for the timer counter that will be called from the
	// interrupt context when the timer expires, specify a pointer to the
	// timer counter driver instance as the callback reference so the handler
	// is able to access the instance data
	XTmrCtr_SetHandler(&tmrctr, TimerCounterHandler, &tmrctr);

	// Enable the interrupt of the timer counter so interrupts will occur
	// and use auto reload mode such that the timer counter will reload
	// itself automatically and continue repeatedly, without this option
	// it would expire once only
	XTmrCtr_SetOptions(&tmrctr, 0, XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION
	| XTC_DOWN_COUNT_OPTION);

	// Set a reset value for the timer counter such that it will expire
	// when it rolls under to 0, the reset value is loaded
	// into the timer counter when it is started
	XTmrCtr_SetResetValue(&tmrctr, 0, XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ-1);

	// Start the timer counter 
	XTmrCtr_Start(&tmrctr, 0);

	while (1) {
	}
	
	Xil_DCacheDisable();
	Xil_ICacheDisable();

	return 0;
}
Exemplo n.º 26
0
int main()
{
   Xil_ICacheEnable();
   Xil_DCacheEnable();
   
   
   print("---Entering main---\n\r");
   
   {
   	   printf("LEDs and switches\r\n");
   	    XGpio_Initialize(&inGpio,XPAR_AXI_GPIO_1_DEVICE_ID);
   	    XGpio_Initialize(&outGpio,XPAR_AXI_GPIO_0_DEVICE_ID);
   	    XGpio_DiscreteWrite(&outGpio,1,0); // leds off
      }

      {
   	   printf("Deca SPI test\r\n");

   	    if (0 != openspi()){
   	    	printf("Init SPI failed\r\n");
   	    } else {

   			// get switches
   			int sw = XGpio_DiscreteRead(&inGpio,1);
   			XGpio_DiscreteWrite(&outGpio,1,sw);
   			//printf("LED: %x\r\n",XGpio_DiscreteRead(&outGpio,1));

   			switch (sw & 0x7){

   			case 1:
   				printf("SS TWR INIT\r\n");
   				ssTwrInit();
   				break;
   			case 2:
   				printf("SS TWR RESP\r\n");
   				ssTwrResp();
   				break;
   			case 3:
   				printf("Simple TX\r\n");
   				simpleTx();
   				break;
   			case 4:
   				printf("Simple RX\r\n");
   				simpleRx();
   				break;
   			case 5:
   				printf("TX Wait\r\n");
   				txWait();
   				break;
   			case 6:
   				printf("RX Wait\r\n");
   				rxWait();
   				break;
   			default:

   			    /* Reset and initialise DW1000. */
   				reset_DW1000();
   				dwt_initialise(DWT_LOADNONE);
   				/* Configure DW1000. */
   				printf("UBW configuration sequence\r\n");
   				dwt_configure(&config);
   				dwt_configuretxrf(&txconfig);

   				/* Activate continuous wave mode. */
   				dwt_configcwmode(config.chan);

   				/* Wait for the wanted duration of the continuous wave transmission. */
   				printf("Waiting for UBW continuous wave transmission delay: %ds\r\n",CONT_WAVE_DURATION_MS/1000);
   				deca_sleep(CONT_WAVE_DURATION_MS);

   				/* Software reset of the DW1000 to deactivate continuous wave mode and go back to default state. Initialisation and configuration should be run
   				 * again if one wants to get the DW1000 back to normal operation. */
   				dwt_softreset();
   			}

   			printf("Deca test done. press any key\r\n");
   			getchar();
   	    }

      }


   print("---Exiting main---\n\r");
   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}
Exemplo n.º 27
0
/**
 * This main function starts the USB Intrerrupt example.
 *
 *
 * @param	None.
 *
 * @return
 *		- XST_SUCCESS if successful.
 *		- XST_FAILURE if test fails.
 * @note	None.
 *
 *****************************************************************************/
int main()
{
	int Status;
	int Index = 0;
	int Cnt = 0;
	/*
	 * Initialize the USB driver.
	 */
	UsbConfigPtr = XUsb_LookupConfig(USB_DEVICE_ID);
	if (UsbConfigPtr == NULL) {
		return XST_FAILURE;
	}

#ifdef __PPC__

	Xil_ICacheEnableRegion (0x80000001);
	Xil_DCacheEnableRegion (0x80000001);
#endif
#ifdef __MICROBLAZE__
	Xil_ICacheInvalidate();
	Xil_ICacheEnable();


	Xil_DCacheInvalidate();
	Xil_DCacheEnable();
#endif
	Status = XUsb_CfgInitialize(&UsbInstance,
					UsbConfigPtr,
					UsbConfigPtr->BaseAddress);
	if (XST_SUCCESS != Status) {
		return XST_FAILURE;
	}

	/*
	 * Initialize the USB instance as required for the
	 * application.
	 */
	InitUsbInterface(&UsbInstance);

	/*
	 * Set our function address to 0 which is the unenumerated state.
	 */
	Status = XUsb_SetDeviceAddress(&UsbInstance, 0);
	if (XST_SUCCESS != Status) {
		return XST_FAILURE;
	}

	/*
	 * Setup the interrupt handlers.
	 */
	XUsb_IntrSetHandler(&UsbInstance, (void *) UsbIfIntrHandler,
			    &UsbInstance);

	XUsb_EpSetHandler(&UsbInstance, 0,
			  (XUsb_EpHandlerFunc *) Ep0IntrHandler, &UsbInstance);

	XUsb_EpSetHandler(&UsbInstance, 1,
			  (XUsb_EpHandlerFunc *) Ep1IntrHandler, &UsbInstance);

	/*
	 * Setup the interrupt system.
	 */
	Status = SetupInterruptSystem(&UsbInstance);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

	/*
	 * Enable the interrupts.
	 */
	XUsb_IntrEnable(&UsbInstance, XUSB_STATUS_GLOBAL_INTR_MASK |
			XUSB_STATUS_RESET_MASK |
			XUSB_STATUS_SUSPEND_MASK |
			XUSB_STATUS_DISCONNECT_MASK |
			XUSB_STATUS_FIFO_BUFF_RDY_MASK |
			XUSB_STATUS_FIFO_BUFF_FREE_MASK |
			XUSB_STATUS_EP0_BUFF1_COMP_MASK |
			XUSB_STATUS_EP1_BUFF1_COMP_MASK |
			XUSB_STATUS_EP2_BUFF1_COMP_MASK |
			XUSB_STATUS_EP1_BUFF2_COMP_MASK |
			XUSB_STATUS_EP2_BUFF2_COMP_MASK);

	XUsb_Start(&UsbInstance);

	/*
	 * Set the device configuration to unenumerated state.
	 */
	UsbInstance.DeviceConfig.CurrentConfiguration = 0;

	/*
	 * Wait untill the USB device is enumerated.
	 */
	while (!UsbInstance.DeviceConfig.CurrentConfiguration);


	/*
	 * Stop the test if the Stop key is pressed or
	 * device lost enumeration.
	 */
	while (1) {

		if (UsbInstance.Config.DmaEnabled) {
			/* Flush the cache before DMA transfer */
			Xil_DCacheFlushRange((u32)&Hello_wav[Index],(u32)1024);
		}

		if (XUsb_EpDataSend(&UsbInstance, 1, &Hello_wav[Index],
					1024) == XST_SUCCESS){
				Index += 1024;
				Cnt ++;
				if (Cnt >= 9000){
					Cnt =0;
					Index = 0;
				}
			}
	}
	return XST_SUCCESS;
}
Exemplo n.º 28
0
/* Program main loop. */
int main()
{
    int32_t ret;
    int32_t mode = 0;
    float retGain;
    uint64_t retFreqRx;
    uint64_t retFreqTx;
    int32_t fmcSel;
    int32_t i;
    int32_t valArray[17];
    XCOMM_Version boardVersion;
    XCOMM_DefaultInit defInit = {FMC_LPC,		//fmcPort
    							 XILINX_ML605,	//carrierBoard
                                 100000000,		//adcSamplingRate
                                 122880000,		//dacSamplingRate
								 10000,			//rxGain1000
								 2400000000ull, //rxFrequency
								 2400000000ull};//txFrequency

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    xil_printf("Running XCOMM Test Program\n\r");

    if(defInit.carrierBoard == XILINX_ZC702)
    {
    	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7 : IICSEL_B1HPC_PS7);
    }
    else
    {
        if(defInit.carrierBoard == XILINX_ZC706)
        {
        	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7_ZC706 :
        										   IICSEL_B1HPC_PS7_ZC706);
        }
        else
        {
        	fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_AXI : IICSEL_B1HPC_AXI);
        }
    }

    xil_printf("\n\rInitializing XCOMM I2C...\n\r");
    ret = XCOMM_InitI2C(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Init I2C Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Init I2C OK!\n\r");
	}

    xil_printf("\n\rGetting XCOMM Revision...\n\r");
    boardVersion = XCOMM_GetBoardVersion(XCOMM_ReadMode_FromHW);
    if(boardVersion.error == -1)
    {
    	xil_printf("\n\rGetting XCOMM Revision Failed!\n\r");
    }
    else
    {
    	xil_printf("Board Version: %s\n\r", boardVersion.value);
    }

    xil_printf("\n\rInitializing XCOMM Components...\n\r");
    ret = XCOMM_Init(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Init OK!\n\r");
	}

	xil_printf("\n\rInitializing the Rx path...\n\r");
	ret = XCOMM_InitRx(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Rx Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Rx Init OK!\n\r");
	}

	xil_printf("\n\rInitializing the Tx path...\n\r");
	ret = XCOMM_InitTx(&defInit);
	if(ret < 0)
	{
		xil_printf("XCOMM Tx Init Failed!\n\r");
		return 0;
	}
	else
	{
		xil_printf("XCOMM Tx Init OK!\n\r");
	}

	xil_printf("\n\rADC sampling rate [Hz]: ");
	ret = XCOMM_GetAdcSamplingRate(XCOMM_ReadMode_FromHW);
	xil_printf("%d \n\r", ret);

	xil_printf("\n\rDAC sampling rate [Hz]: ");
	ret = XCOMM_GetDacSamplingRate(XCOMM_ReadMode_FromHW);
	xil_printf("%d \n\r", ret);

	xil_printf("\n\rDAC available interpolation frequencies [Hz]: ");
	XCOMM_GetDacAvailableInterpolationFreq(valArray);
	i = 0;
	while((valArray[i] != 0) && (i < 5))
	{
		xil_printf("%d ", valArray[i]);
		i++;
	}
	xil_printf("\n\r");

	xil_printf("\n\rDAC available center shift frequencies [Hz]: ");
	XCOMM_GetDacAvailableCenterShiftFreq(valArray);
	i = 0;
	while((valArray[i] != -1) && (i < 17))
	{
		xil_printf("%d ", valArray[i]);
		i++;
	}
	xil_printf("\n\r");

    xil_printf("\n\rTesting the ADC communication... \n\r");
    XCOMM_SetAdcTestMode(0x01, XCOMM_AdcChannel_All);
    adc_capture(fmcSel, 1024, DDR_BASEADDR);

	for (mode = 0x1; mode <= 0x7; mode++)
	{
		XCOMM_SetAdcTestMode(mode, XCOMM_AdcChannel_All);
		adc_test(fmcSel, mode, 0x1);
	}
    xil_printf("ADC test complete.\n\r");

    xil_printf("\n\rTesting the DAC communication... \n\r");
    dac_test(fmcSel);
    xil_printf("DAC test complete.\n\r");

	xil_printf("\n\rSetting the VGA gain to: %d.%d dB\n\r", (int)defInit.rxGain1000/1000, (int)((defInit.rxGain1000 - (int)(defInit.rxGain1000/1000)*1000)));
	retGain = (float)XCOMM_SetRxGain(defInit.rxGain1000) / 1000.0f;
	xil_printf("Actual set VGA gain: %d.%d dB\n\r", (int)retGain, (int)((retGain - (int)retGain) * 1000));

	xil_printf("\n\rSetting the Rx frequency to: %lld%06lld\n\r", defInit.rxFrequency/(uint64_t)1e6, defInit.rxFrequency%(uint64_t)1e6);
    retFreqRx = XCOMM_SetRxFrequency(defInit.rxFrequency);
    xil_printf("Actual set Rx frequency: %lld%06lld\n\r", retFreqRx/(uint64_t)1e6, retFreqRx%(uint64_t)1e6);

	xil_printf("\n\rSetting the Tx frequency to: %lld%06lld\n\r", defInit.txFrequency/(uint64_t)1e6, defInit.txFrequency%(uint64_t)1e6);
    retFreqTx = XCOMM_SetTxFrequency(defInit.txFrequency);
    xil_printf("Actual set Tx frequency: %lld%06lld\n\r", retFreqTx/(uint64_t)1e6, retFreqTx%(uint64_t)1e6);

    xil_printf("\n\rSetting up the DDS... \n\r");
    dds_setup(fmcSel, 5, 5);
    xil_printf("DDS setup complete.\n\r");

    xil_printf("\n\rReading data from air... \n\r");
    XCOMM_SetAdcTestMode(XCOMM_AdcTestMode_Off, XCOMM_AdcChannel_All);
    while(1)
    {
    	adc_capture(fmcSel, 1024, DDR_BASEADDR);
    }
    xil_printf("Read data from air complete. \n\r");

    xil_printf("\n\rFinished XCOMM Test Program\n\r");

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
int main()
{

    static XIntc intc;

    Xil_ICacheEnable();
    Xil_DCacheEnable();

    xil_printf("Testing UART output.\r\n");

    // Camera DMA Configuration
    XAxiDma_Config *dmaconf = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
    XAxiDma dma;
    XAxiDma_CfgInitialize(&dma, dmaconf);
    XAxiDma_Resume(&dma);
    XAxiDma_Reset(&dma);
    while(!XAxiDma_ResetIsDone(&dma));

    // Initialize Video
    InitVideo();

    // Example camera DMA read
    // Note - transfer MUST be 4096B
    // Data format is 20-bit pixel number (stored in a 32 bit integer) followed by 16-bit RGB values
    // This will not work until you implement camera_stream.v.
    // (or at least, until you have it barely working)
    //int resdde = XAxiDma_SimpleTransfer(&dma, (u32)((unsigned char*)&camera), 4096, XAXIDMA_DEVICE_TO_DMA);
    //while(XAxiDma_Busy(&dma,XAXIDMA_DEVICE_TO_DMA));


    int Status;
    XEmacLite *EmacLiteInstPtr = &EmacLiteInstance;
    u32 PhyAddress = 0;
    RecvFrameLength = 0;
    XEmacLite_Config *ConfigPtr;

    /*
     * Initialize the EmacLite device.
     */
    ConfigPtr = XEmacLite_LookupConfig(XPAR_ETHERNET_LITE_DEVICE_ID);
    if (ConfigPtr == NULL) {
        return XST_FAILURE;
    }
    Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,
                    ConfigPtr,
                    ConfigPtr->BaseAddress);
    if (Status != XST_SUCCESS) {
        return XST_FAILURE;
    }

    /*
     * Set the MAC address.
     */
    XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);

    /*
     * Empty any existing receive frames.
     */
    XEmacLite_FlushReceive(EmacLiteInstPtr);

    /*
     * Check if there is a TX buffer available, if there isn't it is an
     * error.
     */
    if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {
        return XST_FAILURE;
    }

    /*
     * Reset the receive frame length to zero.
     */
    RecvFrameLength = 0;

    // Example program that sends packets and changes the color of an on-screen box upon receiving a packet.
    unsigned char c = 0;
    unsigned char r=0xFF, g=0x0, b=0x0;

    while(1) {
        c++;
        if(XEmacLite_IsTxDone(ConfigPtr->BaseAddress)) {
            Status = EmacLiteSendFrame(EmacLiteInstPtr, EMACLITE_TEST_FRAME_SIZE);
            if (Status != XST_SUCCESS) {
                if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {
                    return XST_FAILURE;
                }
            }
        }
        else {
            RecvFrameLength = XEmacLite_Recv(EmacLiteInstPtr, (u8 *)RxFrame);
            if (RecvFrameLength > 0) {
            	xil_printf("Received a packet!\r\n");
                unsigned char oldr = r;
                r=g;
                g=b;
                b=oldr;
            }
            // Example of writing data to the screen
            int x, y;
            for (x = 0; x < 20; x++)
                for (y = 0; y < 20; y++)
                    if (t[y*20 + x]) {
                        fptr[y*640*4 + x*4] = b;
                        fptr[y*640*4 + x*4 + 1] = g;
                        fptr[y*640*4 + x*4 + 2] = r;
                    }
        }
    }

    Xil_DCacheDisable();
    Xil_ICacheDisable();

    return 0;
}
Exemplo n.º 30
0
int main() 
{

   static XIntc intc;
   static XSpi axi_spi_0_Spi;
   static XTmrCtr axi_timer_0_Timer;

   Xil_ICacheEnable();
   Xil_DCacheEnable();

   print("---Entering main---\n\r");

   

   {
      int status;
      
      print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
      
      status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
      
      if (status == 0) {
         print("IntcSelfTestExample PASSED\r\n");
      }
      else {
         print("IntcSelfTestExample FAILED\r\n");
      }
   } 
	
   {
       int Status;

       Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
       if (Status == 0) {
          print("Intc Interrupt Setup PASSED\r\n");
       } 
       else {
         print("Intc Interrupt Setup FAILED\r\n");
      } 
   }
   

   {
      XStatus status;
      
      print("\r\n Runnning SpiSelfTestExample() for axi_spi_0...\r\n");
      
      status = SpiSelfTestExample(XPAR_AXI_SPI_0_DEVICE_ID);
      
      if (status == 0) {
         print("SpiSelfTestExample PASSED\r\n");
      }
      else {
         print("SpiSelfTestExample FAILED\r\n");
      }
   }
    {
       XStatus Status;

       print("\r\n Running Interrupt Test for axi_spi_0...\r\n");

       Status = SpiIntrExample(&intc, &axi_spi_0_Spi, \
                                XPAR_AXI_SPI_0_DEVICE_ID, \
                                XPAR_MICROBLAZE_0_INTC_AXI_SPI_0_IP2INTC_IRPT_INTR);
      if (Status == 0) {
         print("Spi Interrupt Test PASSED\r\n");
      } 
      else {
         print("Spi Interrupt Test FAILED\r\n");
      }

    }
   

   {
      int status;
      
      print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
      
      status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
      
      if (status == 0) {
         print("TmrCtrSelfTestExample PASSED\r\n");
      }
      else {
         print("TmrCtrSelfTestExample FAILED\r\n");
      }
   }
   {
      int Status;

      print("\r\n Running Interrupt Test  for axi_timer_0...\r\n");
      
      Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
                                 XPAR_AXI_TIMER_0_DEVICE_ID, \
                                 XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
	
      if (Status == 0) {
         print("Timer Interrupt Test PASSED\r\n");
      } 
      else {
         print("Timer Interrupt Test FAILED\r\n");
      }

   }
   

   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for be2fe_console0...\r\n");
      status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE0_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   

   {
      int status;
      
      print("\r\nRunning UartLiteSelfTestExample() for be2fe_console1...\r\n");
      status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE1_DEVICE_ID);
      if (status == 0) {
         print("UartLiteSelfTestExample PASSED\r\n");
      }
      else {
         print("UartLiteSelfTestExample FAILED\r\n");
      }
   }
   
   /*
    * Peripheral SelfTest will not be run for debug_module
    * because it has been selected as the STDOUT device
    */


   print("---Exiting main---\n\r");

   Xil_DCacheDisable();
   Xil_ICacheDisable();

   return 0;
}