void kanga_moja(int port, int val)
{
/* does this really work, or is there a problem with the PSG code,
it seems like one channel is completely missing from the output
*/
Z80_Regs regs;
Z80_GetRegs(®s);
if (regs.BC.D==0x8000)
AY8910_control_port_0_w(port,val);
else /* it must be 0x7000 ;-) -V- */
AY8910_write_port_0_w(port,val);
}
void cpu_run(void)
{
int totalcpu,usres;
unsigned char *ROM0; /* opcode decryption is currently supported only for the first memory region */
ROM0 = ROM;
/* count how many CPUs we have to emulate */
totalcpu = 0;
while (totalcpu < MAX_CPU)
{
const struct MemoryReadAddress *mra;
const struct MemoryWriteAddress *mwa;
if (Machine->drv->cpu[totalcpu].cpu_type == 0) break;
/* if sound is disabled, don't emulate the audio CPU */
if (play_sound == 0 && (Machine->drv->cpu[totalcpu].cpu_type & CPU_AUDIO_CPU))
cpurunning[totalcpu] = 0;
else
cpurunning[totalcpu] = 1;
/* initialize the memory base pointers for memory hooks */
RAM = Machine->memory_region[Machine->drv->cpu[totalcpu].memory_region];
mra = Machine->drv->cpu[totalcpu].memory_read;
while (mra->start != -1)
{
if (mra->base) *mra->base = &RAM[mra->start];
mra++;
}
mwa = Machine->drv->cpu[totalcpu].memory_write;
while (mwa->start != -1)
{
if (mwa->base) *mwa->base = &RAM[mwa->start];
mwa++;
}
totalcpu++;
}
#ifdef BUGS
extern void g_exec(void);
g_exec();
#else // BUGS
reset:
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
int cycles;
cycles = Machine->drv->cpu[activecpu].cpu_clock /
(Machine->drv->frames_per_second * Machine->drv->cpu[activecpu].interrupts_per_frame);
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_Reset();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = Z80_IGNORE_INT;
}
break;
#if 0
case CPU_M6502:
{
M6502 *ctxt;
ctxt = (M6502 *)cpucontext[activecpu];
/* Reset6502() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
ctxt->IPeriod = cycles; /* must be done before Reset6502() */
Reset6502(ctxt);
}
break;
case CPU_I86:
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
I86_Reset(RAM,cycles);
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
/* m6809_reset() needs to read memory to get the PC start address */
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
memoryread = Machine->drv->cpu[activecpu].memory_read;
m6809_IPeriod = cycles;
m6809_reset();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = cycles;
ctxt->iperiod = cycles;
ctxt->irq = INT_NONE;
}
break;
#endif
/* ...DS */
}
}
do
{
for (activecpu = 0; activecpu < totalcpu; activecpu++)
{
if (cpurunning[activecpu])
{
int loops;
memoryread = Machine->drv->cpu[activecpu].memory_read;
memorywrite = Machine->drv->cpu[activecpu].memory_write;
RAM = Machine->memory_region[Machine->drv->cpu[activecpu].memory_region];
/* opcode decryption is currently supported only for the first memory region */
if (activecpu == 0) ROM = ROM0;
else ROM = RAM;
switch(Machine->drv->cpu[activecpu].cpu_type & ~CPU_FLAGS_MASK)
{
case CPU_Z80:
{
struct z80context *ctxt;
ctxt = (struct z80context *)cpucontext[activecpu];
Z80_SetRegs(&ctxt->regs);
Z80_ICount = ctxt->icount;
Z80_IPeriod = ctxt->iperiod;
Z80_IRQ = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Z80_Execute();
Z80_GetRegs(&ctxt->regs);
ctxt->icount = Z80_ICount;
ctxt->iperiod = Z80_IPeriod;
ctxt->irq = Z80_IRQ;
}
break;
#if 0
case CPU_M6502:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
Run6502((M6502 *)cpucontext[activecpu]);
break;
case CPU_I86:
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
I86_Execute();
break;
/* DS... */
case CPU_M6809:
{
struct m6809context *ctxt;
ctxt = (struct m6809context *)cpucontext[activecpu];
m6809_SetRegs(&ctxt->regs);
m6809_ICount = ctxt->icount;
m6809_IPeriod = ctxt->iperiod;
m6809_IRequest = ctxt->irq;
for (loops = 0; loops < Machine->drv->cpu[activecpu].interrupts_per_frame; loops++)
m6809_execute();
m6809_GetRegs(&ctxt->regs);
ctxt->icount = m6809_ICount;
ctxt->iperiod = m6809_IPeriod;
ctxt->irq = m6809_IRequest;
}
break;
#endif
/* ...DS */
}
}
}
usres = updatescreen();
if (usres == 2) /* user asked to reset the machine */
goto reset;
} while (usres == 0);
#endif // BUGS
}
int jrpacman_romdecode(int offset)
{
int addressBus = offset;
Z80_Regs Regs;
Z80_GetRegs(&Regs);
{
int m1 = !Regs.M1;//active low (supposedly means opcode read)
/* Pal 8C (16L8) */
int pcbe = !(addressBus >= 0x0000 && addressBus <= 0x3fff ||
addressBus >= 0x8000 && addressBus <=
0xdfff);
int sop0 = !(addressBus >= 0x0000 && addressBus <= 0x001f ||
addressBus >= 0x00e0 && addressBus <=
0x00ff ||
addressBus >= 0x9a60 && addressBus <=
0x9a7f ||
addressBus >= 0x9ac0 && addressBus <=
0x9adf ||
addressBus >= 0x9b60 && addressBus <=
0x9b7f ||
addressBus >= 0x9be0 && addressBus <=
0x9bff && m1);
int sop1 = !(addressBus >= 0x9be0 && addressBus <= 0x9bff && m1 ||
addressBus >= 0x9ca0 && addressBus <=
0x9cbf);
int sop2 = !(addressBus >= 0x00c0 && addressBus <= 0x00df ||
addressBus >= 0x9a40 && addressBus <=
0x9a5f);
/* Pal 9c (16r4) */
int md0 = ByteBit(RAM[addressBus],0);
int md2 = ByteBit(RAM[addressBus],2);
int md7 = ByteBit(RAM[addressBus],7);
int d0 = !( s0 && s1 && !md0 ||
!s0 && s1 && md0 ||
s0 && !s1 && !md0 ||
!s0 && !s1 && !md2);
int d2 = !( s0 && s1 && !md2 ||
!s0 && s1 && !md2 ||
s0 && !s1 && md2 ||
!s0 && !s1 && !md0);
int d7 = !( s2 && s3 ||
!s2 && !md7);
int pb1 = !( sop0 && s0 ||
!sop0 && !s0);
int ns0 = ( sop1 && s0 ||
!sop1 && !s0 ||
!sop0 && sop1);
int ns1 = ( sop1 && s1 && !pb1 ||
!sop1 && s1 && !pb1 ||
sop1 && s1 && pb1 ||
!sop1 && !s1 && pb1 ||
!sop0 && sop1);
int ns2 = ( sop0 && sop1 && s2 ||
sop0 && !sop1 && s2 ||
!sop0 && !sop1 && s2 ||
sop0 && !sop2);
int ns3 = ( !md7 );
// DebugPrint("%04x: %02x & %02x | %02x = %02x",addressBus,RAM[addressBus],~(1<<0) & ~(1<<2) & ~(1<<7), (d0) | (d2<<2) | (d7<<7),(RAM[addressBus] & ~(1<<0) & ~(1<<2) & ~(1<<7)) | (d0) | (d2<<2) | (d7<<7));
/* printf("%04x: %02x & %02x | %02x = %02x\n",addressBus,RAM[addressBus],~(1<<0) & ~(1<<2) & ~(1<<7), (d0) | (d2<<2) | (d7<<7),(RAM[addressBus] & ~(1<<0) & ~(1<<2) & ~(1<<7)) | (d0) | (d2<<2) | (d7<<7));
{static int i=0;
if (i++>100)
{
while (getchar()!='\n')
{}
}}*/
{
int temp= ((int)RAM[addressBus] & 0x7A) | ((d7<<7) | (d2<<2) | (d0));
// if (Z80_Trace==1)
if (!used[addressBus])
{
used[addressBus]=1;
shadowROM[addressBus] = temp;
numberUsed++;
}
else
{
if (shadowROM[addressBus] != temp)
DebugPrint("Address: %04x translates to 2 different values!!!! (%02x and %02x)",addressBus,shadowROM[addressBus],temp);
}
if (Z80_Trace==1)
{
static last = 0;
if (last + 30 <= TickCount()) /* print bnanner if we havent been called in half a second */
printf("m1 sop0 sop1 sop2 pcbe md7 md2 md0 d7 d2 d0 pb1 s0 s1 s2 s3 ns0 ns1 ns2 ns3\n");
last = TickCount();
printf("%-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d %-4d ",
m1, sop0,sop1,sop2,pcbe, md7, md2, md0,
d7, d2, d0, pb1, s0, s1, s2, s3, ns0, ns1, ns2, ns3);
printf("%04x: %02x & %02x | %02x = %02x\n",addressBus,RAM[addressBus],~(1<<0) & ~(1<<2) & ~(1<<7), (d0) | (d2<<2) | (d7<<7),(RAM[addressBus] & ~(1<<0) & ~(1<<2) & ~(1<<7)) | (d0) | (d2<<2) | (d7<<7));
Z80_Trace = 1; /* stop it if it was running for a count */
}
/* latch new flip flops on rising edge of pcbe */
if (!pcbe)
{
s0 = ns0;
s1 = ns1;
s2 = ns2;
s3 = ns3;
}
return temp;
}
}
}
