/*FUNCTION**************************************************************** * * Function Name : _rtc_wait_ms * Returned Value : * Comments : * * wait at least ms_delay ms * *END*********************************************************************/ static void _rtc_wait_ms( uint_32 ms_delay ) { uint_32 us = ms_delay * 1000; uint_32 inst_per_us = BSP_SYSTEM_CLOCK / 1000000; uint_32 inst_to_exec = us * inst_per_us; for (; inst_to_exec != 0; inst_to_exec--) { _ASM_NOP(); } /* Endfor */ }
/*! * \brief This function disables the instruction cache */ void _mcf5441_icache_disable ( void ) { uint32_t tmp = _PSP_GET_CACR(); tmp &= ~(MCF54XX_CACR_IEC); tmp |= MCF54XX_CACR_ICINVA; _PSP_SET_CACR(tmp); // pipeline flush _ASM_NOP(); }
/*! * \brief This function disables the data cache */ void _mcf5441_dcache_disable ( void ) { /* Body */ uint32_t tmp = _PSP_GET_CACR(); _DCACHE_FLUSH(); tmp &= ~(MCF54XX_CACR_DEC); tmp |= MCF54XX_CACR_DCINVA; _PSP_SET_CACR(tmp); // Pipeline flush _ASM_NOP(); } /* Endbody */
void mcf5225_init ( void ) { VMCF5225_STRUCT_PTR reg_ptr = (VMCF5225_STRUCT_PTR)BSP_IPSBAR; uint_8 tmp_8[2]; uint_32 i; /* Disable Software Watchdog Timer */ reg_ptr->SCM.CWCR = 0; /* Enable Program Status Outputs, PST[3:0] signals */ reg_ptr->GPIO.PDDPAR = MCF5225_GPIO_PDDPAR_PST; /* Initialize the PLL ** Divide 48Mhz reference crystal by 6 and multiply by 10 to achieve a ** system clock of 80 Mhz. ** ** To set an MFD of ‘x’ and an RFD of ‘y’, you must first program RFD to ‘y+1’, ** then program MFD to ‘x’, then let the PLL lock, then program RFD to ‘y’. If ** you program RFD simultaneous to MFD, you may over-clock and damage the part. */ reg_ptr->CLK.OCLR = 0xf0; reg_ptr->CLK.CCHR = 5; reg_ptr->CLK.SYNCR = 0 | MCF5225_CLOCK_SYNCR_RFD(0) | MCF5225_CLOCK_SYNCR_MFD(3) | MCF5225_CLOCK_SYNCR_PLLMODE| MCF5225_CLOCK_SYNCR_PLLEN; /* wait for PLL locks before switching clock source */ while (!(reg_ptr->CLK.SYNSR & MCF5225_CLOCK_SYNSR_LOCK)) {} /* now changing clock source is possible */ reg_ptr->CLK.CCLR = 0; reg_ptr->CLK.SYNCR |= MCF5225_CLOCK_SYNCR_CLKSRC; /* wait for PLL lock again */ while (!(reg_ptr->CLK.SYNSR & MCF5225_CLOCK_SYNSR_LOCK)) {} /* Enable on-chip modules to access internal SRAM */ reg_ptr->SCM.RAMBAR = MCF5225_SCM_RAMBAR_BA((uint_32)__INTERNAL_SRAM_BASE) | MCF5225_SCM_RAMBAR_BDE; /* init flexbus */ _bsp_flexbus_setup(); /* init MRAM */ _bsp_flexbus_mram_setup((uint_32)BSP_EXTERNAL_MRAM_BASE); /* Workarround for not problematic PHY reset */ tmp_8[0] = reg_ptr->GPIO.PTIPAR; // save current state tmp_8[1] = reg_ptr->GPIO.PTJPAR; // save current state reg_ptr->GPIO.PTIPAR = 0x00; // Ethernet signals now GPIO reg_ptr->GPIO.PTJPAR = 0x00; // Ethernet signals now GPIO reg_ptr->GPIO.DDRTI = 0xFF; // GPIO output reg_ptr->GPIO.DDRTJ = 0xFF; // GPIO output reg_ptr->GPIO.PORTTI = 0x00; // force Ethernet signals low reg_ptr->GPIO.PORTTJ = 0x00; // force Ethernet signals low reg_ptr->CCM.RCR |= MCF5225_CCM_RCR_FRCRSTOUT; // assert RSTO for (i = 0; i < 10000; i++) _ASM_NOP(); reg_ptr->CCM.RCR &= ~(MCF5225_CCM_RCR_FRCRSTOUT); // negate RSTO for (i = 0; i < 1000000; i++) _ASM_NOP(); reg_ptr->GPIO.PTIPAR = tmp_8[0]; // restore current state reg_ptr->GPIO.PTJPAR = tmp_8[1]; // restore Ethernet signals low }