/*
* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
*/
static void __init omap_map_sram(void)
{
int cached = 1;
if (omap_sram_size == 0)
return;
if (cpu_is_omap34xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
* SDRAM controller disabled, and if it is marked cached,
* the ARM may attempt to write cache lines back to SDRAM
* which will cause the system to hang.
*/
cached = 0;
}
omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
cached);
if (!omap_sram_base) {
pr_err("SRAM: Could not map\n");
return;
}
omap_sram_ceil = omap_sram_base + omap_sram_size;
/*
* Looks like we need to preserve some bootloader code at the
* beginning of SRAM for jumping to flash for reboot to work...
*/
memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
omap_sram_size - SRAM_BOOTLOADER_SZ);
}
/*
* Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
*/
static void __init omap_map_sram(void)
{
int cached = 1;
if (omap_sram_size == 0)
return;
#ifdef CONFIG_OMAP4_ERRATA_I688
omap_sram_start += PAGE_SIZE;
omap_sram_size -= SZ_16K;
#endif
if (cpu_is_omap34xx()) {
/*
* SRAM must be marked as non-cached on OMAP3 since the
* CORE DPLL M2 divider change code (in SRAM) runs with the
* SDRAM controller disabled, and if it is marked cached,
* the ARM may attempt to write cache lines back to SDRAM
* which will cause the system to hang.
*/
cached = 0;
}
omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
cached);
if (!omap_sram_base) {
pr_err("SRAM: Could not map\n");
return;
}
{
/* The first SRAM_BOOTLOADER_SZ of SRAM are reserved */
void *base = (void *)omap_sram_base + SRAM_BOOTLOADER_SZ;
phys_addr_t phys = omap_sram_start + SRAM_BOOTLOADER_SZ;
size_t len = omap_sram_size - SRAM_BOOTLOADER_SZ;
omap_gen_pool = gen_pool_create(ilog2(FNCPY_ALIGN), -1);
if (omap_gen_pool)
WARN_ON(gen_pool_add_virt(omap_gen_pool,
(unsigned long)base, phys, len, -1));
WARN_ON(!omap_gen_pool);
}
/*
* Looks like we need to preserve some bootloader code at the
* beginning of SRAM for jumping to flash for reboot to work...
*/
memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
omap_sram_size - SRAM_BOOTLOADER_SZ);
}
/**
* zynq_pm_remap_ocm() - Remap OCM
* Returns a pointer to the mapped memory or NULL.
*
* Remap the OCM.
*/
static void __iomem *zynq_pm_remap_ocm(void)
{
struct device_node *np;
const char *comp = "xlnx,zynq-ocmc-1.0";
void __iomem *base = NULL;
np = of_find_compatible_node(NULL, NULL, comp);
if (np) {
struct device *dev;
unsigned long pool_addr;
unsigned long pool_addr_virt;
struct gen_pool *pool;
of_node_put(np);
dev = &(of_find_device_by_node(np)->dev);
/* Get OCM pool from device tree or platform data */
pool = gen_pool_get(dev, NULL);
if (!pool) {
pr_warn("%s: OCM pool is not available\n", __func__);
return NULL;
}
pool_addr_virt = gen_pool_alloc(pool, zynq_sys_suspend_sz);
if (!pool_addr_virt) {
pr_warn("%s: Can't get OCM poll\n", __func__);
return NULL;
}
pool_addr = gen_pool_virt_to_phys(pool, pool_addr_virt);
if (!pool_addr) {
pr_warn("%s: Can't get physical address of OCM pool\n",
__func__);
return NULL;
}
base = __arm_ioremap_exec(pool_addr, zynq_sys_suspend_sz,
MT_MEMORY_RWX);
if (!base) {
pr_warn("%s: IOremap OCM pool failed\n", __func__);
return NULL;
}
pr_debug("%s: Remap OCM %s from %lx to %lx\n", __func__, comp,
pool_addr_virt, (unsigned long)base);
} else {
pr_warn("%s: no compatible node found for '%s'\n", __func__,
comp);
}
return base;
}
