void main()
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2803x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the DSP2803x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
EALLOW;
GpioCtrlRegs.GPAPUD.all = 0; // Enable all Pull-ups
GpioCtrlRegs.GPBPUD.all = 0;
GpioCtrlRegs.GPADIR.bit.GPIO1 = 1; // GPIO1 set in the ISR to indicate
// device woken up.
GpioIntRegs.GPIOLPMSEL.bit.GPIO0 = 1; // Choose GPIO0 pin for wakeup
EDIS;
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2803x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.WAKEINT = &WAKE_ISR;
EDIS;
// Step 4. Initialize all the Device Peripherals:
// Not applicable for this example.
// Step 5. User specific code, enable interrupts:
// Enable CPU INT1 which is connected to WakeInt:
IER |= M_INT1;
// Enable WAKEINT in the PIE: Group 1 interrupt 8
PieCtrlRegs.PIEIER1.bit.INTx8 = 1;
PieCtrlRegs.PIEACK.bit.ACK1 = 1;
// Enable global Interrupts:
EINT; // Enable Global interrupt INTM
// Choose qualification cycles in LPMCR0 register
SysCtrlRegs.LPMCR0.bit.QUALSTDBY = 0; // The wakeup signal should be (2+QUALSTDBY) OSCCLKs wide.
// Write the LPM code value
EALLOW;
if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 1) // Only enter Standby mode when PLL is not in limp mode.
{
SysCtrlRegs.LPMCR0.bit.LPM = 0x0001; // LPM mode = Standby
}
EDIS;
// Force device into STANDBY
__asm(" IDLE"); // Device waits in IDLE until falling edge on GPIO0/XNMI pin
// wakes device from Standby mode.
for(;;){} // Loop here after wake-up.
}
/*******************************************************************************
* Function Name : Reset_Delay
* Description : Delay some time
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void Reset_Delay(void)
{
int i=0xff;
while(i--)
__asm("nop");
}
void BeginIO(struct IORequest *iorequest)
{ register struct IORequest *a1 __asm("a1")=iorequest;
register struct Device *a6 __asm("a6")=iorequest->io_Device;
__asm volatile ("jsr a6@(-30:W)" :: "r" (a1), "r" (a6));
}
SemaphoreHandle_t xEMACInit( void )
{
/* Code supplied by Atmel (modified) --------------------*/
/* disable pull up on RXDV => PHY normal mode (not in test mode),
PHY has internal pull down. */
AT91C_BASE_PIOB->PIO_PPUDR = 1 << 15;
#if USE_RMII_INTERFACE != 1
/* PHY has internal pull down : set MII mode. */
AT91C_BASE_PIOB->PIO_PPUDR= 1 << 16;
#endif
/* clear PB18 <=> PHY powerdown. */
AT91F_PIO_CfgOutput( AT91C_BASE_PIOB, 1 << 18 ) ;
AT91F_PIO_ClearOutput( AT91C_BASE_PIOB, 1 << 18) ;
/* After PHY power up, hardware reset. */
AT91C_BASE_RSTC->RSTC_RMR = emacRESET_KEY | emacRESET_LENGTH;
AT91C_BASE_RSTC->RSTC_RCR = emacRESET_KEY | AT91C_RSTC_EXTRST;
/* Wait for hardware reset end. */
while( !( AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL ) )
{
__asm( "NOP" );
}
__asm( "NOP" );
/* EMAC IO init for EMAC-PHY com. Remove EF100 config. */
AT91F_EMAC_CfgPIO();
/* Enable com between EMAC PHY.
Enable management port. */
AT91C_BASE_EMAC->EMAC_NCR |= AT91C_EMAC_MPE;
/* MDC = MCK/32. */
AT91C_BASE_EMAC->EMAC_NCFGR |= ( 2 ) << 10;
/* Wait for PHY auto init end (rather crude delay!). */
vTaskDelay( emacPHY_INIT_DELAY );
/* PHY configuration. */
#if USE_RMII_INTERFACE != 1
{
unsigned long ulControl;
/* PHY has internal pull down : disable MII isolate. */
vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
vReadPHY( AT91C_PHY_ADDR, MII_BMCR, &ulControl );
ulControl &= ~BMCR_ISOLATE;
vWritePHY( AT91C_PHY_ADDR, MII_BMCR, ulControl );
}
#endif
/* Disable management port again. */
AT91C_BASE_EMAC->EMAC_NCR &= ~AT91C_EMAC_MPE;
#if USE_RMII_INTERFACE != 1
/* Enable EMAC in MII mode, enable clock ERXCK and ETXCK. */
AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_CLKEN ;
#else
/* Enable EMAC in RMII mode, enable RMII clock (50MHz from oscillator
on ERFCK). */
AT91C_BASE_EMAC->EMAC_USRIO = AT91C_EMAC_RMII | AT91C_EMAC_CLKEN ;
#endif
/* End of code supplied by Atmel ------------------------*/
/* Setup the buffers and descriptors. */
prvSetupDescriptors();
/* Load our MAC address into the EMAC. */
prvSetupMACAddress();
/* Try to connect. */
if( prvProbePHY() )
{
/* Enable the interrupt! */
prvSetupEMACInterrupt();
}
return xSemaphore;
}
//THE TI VERSION IS UNTESTED!!! (40 is a hardcode)
unsigned long Who(void){
__asm ( " LDR R0, [SP,#40] ; R0 = return address from interrupt\n"
" bx LR\n");
}
unsigned long systemClock()
{
__asm (
"rdtsc;"
);
}
__interrupt void rsvd_ISR(void) // For test
{
__asm (" ESTOP0");
for(;;);
}
long esp(void)
{
__asm("movl %esp,%eax");
}
void platform_idle_hook( void )
{
__asm("wfi");
}
void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
{
uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
TickType_t xModifiableIdleTime;
/* Make sure the SysTick reload value does not overflow the counter. */
if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
{
xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
}
/* Stop the SysTick momentarily. The time the SysTick is stopped for
is accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
/* Calculate the reload value required to wait xExpectedIdleTime
tick periods. -1 is used because this code will execute part way
through one of the tick periods. */
ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
if( ulReloadValue > ulStoppedTimerCompensation )
{
ulReloadValue -= ulStoppedTimerCompensation;
}
/* Enter a critical section but don't use the taskENTER_CRITICAL()
method as that will mask interrupts that should exit sleep mode. */
__asm( " cpsid i" );
__asm( " dsb" );
__asm( " isb" );
/* If a context switch is pending or a task is waiting for the scheduler
to be unsuspended then abandon the low power entry. */
if( eTaskConfirmSleepModeStatus() == eAbortSleep )
{
/* Restart from whatever is left in the count register to complete
this tick period. */
portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Reset the reload register to the value required for normal tick
periods. */
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
/* Re-enable interrupts - see comments above __disable_interrupt()
call above. */
__asm( " cpsie i" );
}
else
{
/* Set the new reload value. */
portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
/* Clear the SysTick count flag and set the count value back to
zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
/* Restart SysTick. */
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
/* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
set its parameter to 0 to indicate that its implementation contains
its own wait for interrupt or wait for event instruction, and so wfi
should not be executed again. However, the original expected idle
time variable must remain unmodified, so a copy is taken. */
xModifiableIdleTime = xExpectedIdleTime;
configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
if( xModifiableIdleTime > 0 )
{
__asm( " dsb" );
__asm( " wfi" );
__asm( " isb" );
}
configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
/* Stop SysTick. Again, the time the SysTick is stopped for is
accounted for as best it can be, but using the tickless mode will
inevitably result in some tiny drift of the time maintained by the
kernel with respect to calendar time. */
ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
/* Re-enable interrupts - see comments above __disable_interrupt()
call above. */
__asm( " cpsie i" );
if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
{
uint32_t ulCalculatedLoadValue;
/* The tick interrupt has already executed, and the SysTick
count reloaded with ulReloadValue. Reset the
portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
period. */
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
/* Don't allow a tiny value, or values that have somehow
underflowed because the post sleep hook did something
that took too long. */
if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
{
ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
}
portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
/* The tick interrupt handler will already have pended the tick
processing in the kernel. As the pending tick will be
processed as soon as this function exits, the tick value
maintained by the tick is stepped forward by one less than the
time spent waiting. */
ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
}
else
{
/* Something other than the tick interrupt ended the sleep.
Work out how long the sleep lasted rounded to complete tick
periods (not the ulReload value which accounted for part
ticks). */
ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
/* How many complete tick periods passed while the processor
was waiting? */
ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
/* The reload value is set to whatever fraction of a single tick
period remains. */
portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
}
/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
value. The critical section is used to ensure the tick interrupt
can only execute once in the case that the reload register is near
zero. */
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
portENTER_CRITICAL();
{
portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
vTaskStepTick( ulCompleteTickPeriods );
portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
}
portEXIT_CRITICAL();
}
}
static unsigned long stop_mode_power_down_hook( unsigned long sleep_ms )
{
unsigned long retval;
unsigned long wut_ticks_passed;
unsigned long scale_factor = 0;
UNUSED_PARAMETER(sleep_ms);
UNUSED_PARAMETER(rtc_timeout_start_time);
UNUSED_PARAMETER(scale_factor);
if ( ( ( SCB->SCR & (unsigned long)SCB_SCR_SLEEPDEEP_Msk) != 0) && sleep_ms < 5 ){
SCB->SCR &= (~((unsigned long)SCB_SCR_SLEEPDEEP_Msk));
__asm("wfi");
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Note: We return 0 ticks passed because system tick is still going when wfi instruction gets executed */
ENABLE_INTERRUPTS;
return 0;
}
if ( ( ( SCB->SCR & (unsigned long)SCB_SCR_SLEEPDEEP_Msk) ) != 0 )
{
/* pick up the appropriate prescaler for a requested delay */
select_wut_prescaler_calculate_wakeup_time(&rtc_timeout_start_time, sleep_ms, &scale_factor );
DISABLE_INTERRUPTS;
SysTick->CTRL &= (~(SysTick_CTRL_TICKINT_Msk|SysTick_CTRL_ENABLE_Msk)); /* systick IRQ off */
RTC_ITConfig(RTC_IT_WUT, ENABLE);
EXTI_ClearITPendingBit( RTC_INTERRUPT_EXTI_LINE );
PWR_ClearFlag(PWR_FLAG_WU);
RTC_ClearFlag(RTC_FLAG_WUTF);
RTC_SetWakeUpCounter( rtc_timeout_start_time );
RTC_WakeUpCmd( ENABLE );
platform_rtc_enter_powersave();
DBGMCU->CR |= 0x03; /* Enable debug in stop mode */
/* This code will be running with BASEPRI register value set to 0, the main intention behind that is that */
/* all interrupts must be allowed to wake the CPU from the power-down mode */
/* the PRIMASK is set to 1( see DISABLE_INTERRUPTS), thus we disable all interrupts before entering the power-down mode */
/* This may sound contradictory, however according to the ARM CM3 documentation power-management unit */
/* takes into account only the contents of the BASEPRI register and it is an external from the CPU core unit */
/* PRIMASK register value doesn't affect its operation. */
/* So, if the interrupt has been triggered just before the wfi instruction */
/* it remains pending and wfi instruction will be treated as a nop */
__asm("wfi");
/* After CPU exits powerdown mode, the processer will not execute the interrupt handler(PRIMASK is set to 1) */
/* Disable rtc for now */
RTC_WakeUpCmd( DISABLE );
RTC_ITConfig(RTC_IT_WUT, DISABLE);
/* Initialise the clocks again */
init_clocks( );
/* Enable CPU ticks */
SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk|SysTick_CTRL_ENABLE_Msk);
/* Get the time of how long the sleep lasted */
wut_ticks_passed = rtc_timeout_start_time - RTC_GetWakeUpCounter();
UNUSED_VARIABLE(wut_ticks_passed);
platform_rtc_exit_powersave( sleep_ms, (uint32_t *)&retval );
/* as soon as interrupts are enabled, we will go and execute the interrupt handler */
/* which triggered a wake up event */
ENABLE_INTERRUPTS;
wake_up_interrupt_triggered = false;
UNUSED_VARIABLE(wake_up_interrupt_triggered);
return retval;
}
else
{
UNUSED_PARAMETER(wut_ticks_passed);
ENABLE_INTERRUPTS;
__asm("wfi");
/* Note: We return 0 ticks passed because system tick is still going when wfi instruction gets executed */
return 0;
}
}
/*
* ======== PowerMSP432_policyFxn ========
*/
void PowerMSP432_policyFxn()
{
UInt constraints;
Bool slept = false;
UInt taskKey;
UInt swiKey;
/* disable interrupts */
CPU_cpsid();
/* disable Swi and Task scheduling */
swiKey = Swi_disable();
taskKey = Task_disable();
/* query the declared constraints */
constraints = Power_getConstraintMask();
/*
* Check if can go to a sleep state, starting with the deepest level.
* Do not go to a sleep state if a lesser sleep state is disallowed.
*/
/* check if can go to DEEPSLEEP_1 */
if ((constraints & ((1 << PowerMSP432_DISALLOW_SLEEP) |
(1 << PowerMSP432_DISALLOW_DEEPSLEEP_0) |
(1 << PowerMSP432_DISALLOW_DEEPSLEEP_1))) == 0) {
/* go to DEEPSLEEP_1 */
Power_sleep(PowerMSP432_DEEPSLEEP_1);
/* set 'slept' to true*/
slept = true;
}
/* if didn't sleep yet, now check if can go to DEEPSLEEP_0 */
if (!slept && ((constraints & ((1 << PowerMSP432_DISALLOW_SLEEP) |
(1 << PowerMSP432_DISALLOW_DEEPSLEEP_0))) == 0)) {
/* go to DEEPSLEEP_0 */
Power_sleep(PowerMSP432_DEEPSLEEP_0);
/* set 'slept' to true*/
slept = true;
}
/* if didn't sleep yet, now check if can go to SLEEP */
if (!slept && ((constraints & (1 << PowerMSP432_DISALLOW_SLEEP)) == 0)) {
/* go to SLEEP */
Power_sleep(PowerMSP432_SLEEP);
/* set 'slept' to true*/
slept = true;
}
/* re-enable interrupts */
CPU_cpsie();
/* restore Swi scheduling */
Swi_restore(swiKey);
/* restore Task scheduling */
Task_restore(taskKey);
/* if didn't sleep yet, just do WFI */
if (!slept) {
__asm(" wfi");
}
}
static void wait_jtag() {
while(1) {
__asm("");
}
}
/**
* @brief Advance the TAP to the requested state
*
* @param[in] target The state to get the TAP into
*/
void jtagTAP_SetState(jtagTAP_TAPState target)
{
if(target != JTAGTAP_STATE_UNKNOWN)
{
if((target == JTAGTAP_STATE_RESET) && (jtag_IsAllocated(JTAG_SIGNAL_TRST)))
{
unsigned int count = 0;
//take the easy way to reset
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Set(JTAG_SIGNAL_TRST, false); //Assumes an active low signal
//delay a bit
while(++count < delay_count)
{
__asm("nop");
}
jtag_Set(JTAG_SIGNAL_TRST, true); //Assumes an active low signal
TAPState = JTAGTAP_STATE_RESET;
}
while(TAPState != target)
{
//only process if there is a state change requested.
switch(TAPState)
{
//Handle the unknown case by performing a reset
case JTAGTAP_STATE_UNKNOWN:
if(jtag_IsAllocated(JTAG_SIGNAL_TRST))
{
unsigned int count = 0;
//take the easy way to reset
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Set(JTAG_SIGNAL_TRST, false); //Assumes an active low signal
//delay a bit
while(++count < delay_count)
{
__asm("nop");
}
jtag_Set(JTAG_SIGNAL_TRST, true); //Assumes an active low signal
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
jtag_Clock();
jtag_Clock();
jtag_Clock();
jtag_Clock();
}
TAPState = JTAGTAP_STATE_RESET;
break;
case JTAGTAP_STATE_RESET:
jtag_Set(JTAG_SIGNAL_TMS, false);
jtag_Clock();
TAPState = JTAGTAP_STATE_IDLE;
break;
case JTAGTAP_STATE_IDLE:
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
TAPState = JTAGTAP_STATE_DR_SCAN;
break;
case JTAGTAP_STATE_DR_SCAN:
if((target >= JTAGTAP_STATE_DR_CAPTURE) && (target <= JTAGTAP_STATE_DR_UPDATE))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_DR_CAPTURE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_IR_SCAN;
}
jtag_Clock();
break;
case JTAGTAP_STATE_DR_CAPTURE:
if(target == JTAGTAP_STATE_DR_SHIFT)
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_DR_SHIFT;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_DR_EXIT1;
}
jtag_Clock();
break;
case JTAGTAP_STATE_DR_SHIFT:
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
TAPState = JTAGTAP_STATE_DR_EXIT1;
break;
case JTAGTAP_STATE_DR_EXIT1:
if((target == JTAGTAP_STATE_DR_PAUSE) || (target == JTAGTAP_STATE_DR_EXIT2) || (target == JTAGTAP_STATE_DR_SHIFT))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_DR_PAUSE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_DR_UPDATE;
}
jtag_Clock();
break;
case JTAGTAP_STATE_DR_PAUSE:
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
TAPState = JTAGTAP_STATE_DR_EXIT2;
break;
case JTAGTAP_STATE_DR_EXIT2:
if((target == JTAGTAP_STATE_DR_PAUSE) || (target == JTAGTAP_STATE_DR_EXIT1) || (target == JTAGTAP_STATE_DR_SHIFT))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_DR_SHIFT;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_DR_UPDATE;
}
jtag_Clock();
break;
case JTAGTAP_STATE_DR_UPDATE:
if(target == JTAGTAP_STATE_IDLE)
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IDLE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_DR_SCAN;
}
jtag_Clock();
break;
case JTAGTAP_STATE_IR_SCAN:
if((target >= JTAGTAP_STATE_IR_CAPTURE) && (target <= JTAGTAP_STATE_IR_UPDATE))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IR_CAPTURE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_RESET;
}
jtag_Clock();
break;
case JTAGTAP_STATE_IR_CAPTURE:
if(target == JTAGTAP_STATE_IR_SHIFT)
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IR_SHIFT;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_IR_EXIT1;
}
jtag_Clock();
break;
case JTAGTAP_STATE_IR_SHIFT:
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
TAPState = JTAGTAP_STATE_IR_EXIT1;
break;
case JTAGTAP_STATE_IR_EXIT1:
if((target == JTAGTAP_STATE_IR_PAUSE) || (target == JTAGTAP_STATE_IR_EXIT2) || (target == JTAGTAP_STATE_IR_SHIFT))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IR_PAUSE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_IR_UPDATE;
}
jtag_Clock();
break;
case JTAGTAP_STATE_IR_PAUSE:
jtag_Set(JTAG_SIGNAL_TMS, true);
jtag_Clock();
TAPState = JTAGTAP_STATE_IR_EXIT2;
break;
case JTAGTAP_STATE_IR_EXIT2:
if((target == JTAGTAP_STATE_IR_PAUSE) || (target == JTAGTAP_STATE_IR_EXIT1) || (target == JTAGTAP_STATE_IR_SHIFT))
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IR_SHIFT;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_IR_UPDATE;
}
jtag_Clock();
break;
case JTAGTAP_STATE_IR_UPDATE:
if(target == JTAGTAP_STATE_IDLE)
{
jtag_Set(JTAG_SIGNAL_TMS, false);
TAPState = JTAGTAP_STATE_IDLE;
}
else
{
jtag_Set(JTAG_SIGNAL_TMS, true);
TAPState = JTAGTAP_STATE_DR_SCAN;
}
jtag_Clock();
break;
}
}
}
else
{
TAPState = JTAGTAP_STATE_UNKNOWN;
}
}
void _exit(int status)
{
/* disable all interrupts, run infinite loop */
__asm("cpsid i");
while(1);
}
void IfxCpu_Trap_systemCall_Cpu5(uint32 tin)
{
trapWatch = IfxCpu_Trap_extractTrapInfo(IfxCpu_Trap_Class_systemCall, tin);
IFX_CFG_CPU_TRAP_SYSCALL_CPU5_HOOK(trapWatch);
__asm("rfe");
}
/*
* ======== Power_doWFI ========
*/
Void Power_doWFI()
{
__asm(" wfi");
}
/* This is a hand written Thumb-2 assembly language version of the
algorithm 3 version of lwip_standard_chksum in lwIP's inet_chksum.c. It
performs the checksumming 32-bits at a time and even unrolls the loop to
perform two of these 32-bit adds per loop iteration.
Returns:
16-bit 1's complement summation (not inversed).
NOTE: This function does return a uint16_t from the assembly language code
but is marked as void so that GCC doesn't issue warning because it
doesn't know about this low level return.
*/
__attribute__((naked)) void /*uint16_t*/ thumb2_checksum(const void* pData, int length)
{
__asm (
".syntax unified\n"
".thumb\n"
// Push non-volatile registers we use on stack. Push link register too to
// keep stack 8-byte aligned and allow single pop to restore and return.
" push {r4, lr}\n"
// Initialize sum, r2, to 0.
" movs r2, #0\n"
// Remember whether pData was at odd address in r3. This is used later to
// know if it needs to swap the result since the summation will be done at
// an offset of 1, rather than 0.
" ands r3, r0, #1\n"
// Need to 2-byte align? If not skip ahead.
" beq 1$\n"
// We can return if there are no bytes to sum.
" cbz r1, 9$\n"
// 2-byte align.
// Place the first data byte in odd summation location since it needs to be
// swapped later. It's ok to overwrite r2 here as it only had a value of 0
// up until now. Advance r0 pointer and decrement r1 length as we go.
" ldrb r2, [r0], #1\n"
" lsls r2, r2, #8\n"
" subs r1, r1, #1\n"
// Need to 4-byte align? If not skip ahead.
"1$:\n"
" ands r4, r0, #3\n"
" beq 2$\n"
// Have more than 1 byte left to align? If not skip ahead to take care of
// trailing byte.
" cmp r1, #2\n"
" blt 7$\n"
// 4-byte align.
" ldrh r4, [r0], #2\n"
" adds r2, r2, r4\n"
" subs r1, r1, #2\n"
// Main summing loop which sums up data 2 words at a time.
// Make sure that we have more than 7 bytes left to sum.
"2$:\n"
" cmp r1, #8\n"
" blt 3$\n"
// Sum next two words. Applying previous upper 16-bit carry to
// lower 16-bits.
" ldr r4, [r0], #4\n"
" adds r2, r4\n"
" adc r2, r2, #0\n"
" ldr r4, [r0], #4\n"
" adds r2, r4\n"
" adc r2, r2, #0\n"
" subs r1, r1, #8\n"
" b 2$\n"
// Sum up any remaining half-words.
"3$:\n"
// Make sure that we have more than 1 byte left to sum.
" cmp r1, #2\n"
" blt 7$\n"
// Sum up next half word, continue to apply carry.
" ldrh r4, [r0], #2\n"
" adds r2, r4\n"
" adc r2, r2, #0\n"
" subs r1, r1, #2\n"
" b 3$\n"
// Handle trailing byte, if it exists
"7$:\n"
" cbz r1, 8$\n"
" ldrb r4, [r0]\n"
" adds r2, r4\n"
" adc r2, r2, #0\n"
// Fold 32-bit checksum into 16-bit checksum.
"8$:\n"
" ubfx r4, r2, #16, #16\n"
" ubfx r2, r2, #0, #16\n"
" adds r2, r4\n"
" ubfx r4, r2, #16, #16\n"
" ubfx r2, r2, #0, #16\n"
" adds r2, r4\n"
// Swap bytes if started at odd address
" cbz r3, 9$\n"
" rev16 r2, r2\n"
// Return final sum.
"9$: mov r0, r2\n"
" pop {r4, pc}\n"
);
}
__interrupt void PIE_RESERVED(void) // Reserved space. For test.
{
__asm (" ESTOP0");
for(;;);
}
void waitForInterrupt() {
__asm ( "WFI\n" );
}
OSRAMDelay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne OSRAMDelay\n"
" bx lr");
}
/* application. */
void resetISR(void)
{
/* Jump to the CCS C Initialization Routine. */
__asm(" .global _c_int00\n"
" b.w _c_int00");
}
//Code Composer Studio Code
void Delay(unsigned long ulCount){
__asm ( " subs r0, #1\n"
" bne Delay\n"
" bx lr\n");
}
void Fail()
{
__asm(" ESTOP0");
}
/*******************************************************************************
* Function Name : Delay
* Description : Delay some time.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void Delay(void)
{
int i=0xf;
while(i--)
__asm("nop");
}
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2803x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the DSP2803x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
InitEPwm3Gpio();
InitECap1Gpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2803x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2803x_DefaultIsr.c.
// This function is found in DSP2803x_PieVect.c.
InitPieVectTable();
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.ECAP1_INT = &ecap1_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
InitEPwmTimer(); // For this example, only initialize the ePWM Timers
InitECapture();
// Step 5. User specific code, enable interrupts:
// Initialize counters:
ECap1IntCount = 0;
ECap1PassCount = 0;
// Enable CPU INT4 which is connected to ECAP1-4 INT:
IER |= M_INT4;
// Enable eCAP INTn in the PIE: Group 3 interrupt 1-6
PieCtrlRegs.PIEIER4.bit.INTx1 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
__asm(" NOP");
}
}
/*******************************************************************************
* Function Name : Power_Delay
* Description : Delay some time for power up.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
static void Power_Delay(void)
{
unsigned long i=0x4fff;
while(i--)
__asm("nop");
}
static unsigned long
getrbp() {
__asm("movq %rbp, %rax\n");
}
void
ka53_cache_enable(void)
{
int start, s**t;
/*
* Turn caches off.
*/
mtpr(0, PR_ICSR);
mtpr(0, PR_PCCTL);
mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
/*
* Invalidate caches.
*/
mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
start = 0x01400000;
s**t = 0x01420000;
/* Flush cache lines */
for (; start < s**t; start += 0x20)
mtpr(0, start);
mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
PR_CCTL);
start = 0x01000000;
s**t = 0x01020000;
/* clear tag and valid */
for (; start < s**t; start += 0x20)
mtpr(0, start);
mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
start = 0x01800000;
s**t = 0x01802000;
/* Clear primary cache */
for (; start < s**t; start += 0x20)
mtpr(0, start);
/* Flush the pipes (via REI) */
__asm("movpsl -(%sp); movab 1f,-(%sp); rei; 1:;");
/* Enable primary cache */
mtpr(PCCTL_P_EN|PCCTL_I_EN|PCCTL_D_EN, PR_PCCTL);
/* Enable the VIC */
start = 0;
s**t = 0x800;
for (; start < s**t; start += 0x20) {
mtpr(start, PR_VMAR);
mtpr(0, PR_VTAG);
}
mtpr(ICSR_ENABLE, PR_ICSR);
}
// Initializes C and starts program
void ResetISR(void)
{
__asm(" .global _c_int00\n"
" b.w _c_int00");
}