// Configures the clock PLL multiplier, this function will use the #define FCY above for the clock rate
void SYS_ConfigureClock(unsigned long FCY)
{
// Save off the clcok rate
g_FCY = FCY;
// We need to initiate a clock switch. This is time critical code so we will use some special built-in
// functions to help us out and unlocks/relocks these registers.
__builtin_write_OSCCONH(0x07); // Select the Fast RC clock with postscaler
__builtin_write_OSCCONL(0x01); // Initiate the switch by setting the switch enable bit
// Wait for Clock Switch to occur
while (OSCCONbits.COSC != 0b111);
// To properly configure the PLL we need to switch between two clocks. First
// start off with a Fast RC clock rate. Then modify the PLLPre,PLLPost,PLLDiv registers,
// to set up the appropriate new clock rate. Then issue a clock switch.
// Check for NTSC
if(g_FCY == FCY_NTSC)
{
// Configures the clock to 24 * Input (NTSC) = 85.90908 MHz or Fcy = 42.95454 MHz
// General Equation for PLL setup = Fosc = Fin ( M / (N1 * N2) )
// M = PLLDIV = 96
// N1 = PLLPRE = 2
// N2 = PLLPOST = 2
CLKDIVbits.PLLPRE = 0; // 0 = 2, 1 = 3, 2 = 4, etc
CLKDIVbits.PLLPOST = 0; // 0 = 2
PLLFBD = 94; // PLL feedback divisor where 0 = 2, 1 = 3, etc
}
else // Must be VGA (In the future the user could add more speeds in here)
{
// Configures the clock to 3.5 * VGA dot clock = 88.1125 MHz or Fcy = 44.05625 MHz
// Actual frequency is Fosc = 88.1463 MHz or Fcy = 44.0731 MHz so clock period is 22.69 nS
// General Equation for PLL setup = Fosc = Fin ( M / (N1 * N2) )
// M = PLLDIV = 197
// N1 = PLLPRE = 4
// N2 = PLLPOST = 2
CLKDIVbits.PLLPRE = 2; // 0 = 2, 1 = 3, 2 = 4, etc
CLKDIVbits.PLLPOST = 0; // 0 = 2
PLLFBD = 195; // PLL feedback divisor where 0 = 2, 1 = 3, etc
}
// We need to initiate a clock switch. This is time critical code so we will use some special built-in
// functions to help us out and unlocks/relocks these registers.
__builtin_write_OSCCONH(0x03); // Select the External Clock with PLL
__builtin_write_OSCCONL(0x01); // Initiate the switch by setting the switch enable bit
// Wait for Clock Switch to occur
while (OSCCONbits.COSC != 0b011);
// Wait for PLL to lock
while (OSCCONbits.LOCK != 1);
}
/*******************************************************************************
* Function: changeClockFreq
* Inputs: <unsigned char mhz> desired new frequency of internal clock
* Outputs: None
* Description: This function assumes an 8MHz XT oscillator is connected to
* the microcontroller. It uses the PLL module to allow the user
* to select a frequency between 15MHz and 140MHz. Note that
* rounding may occur at 80-140MHz freqencies. Clock switching
* takes about 1.6ms to complete and may be performed as many
* times as desired.
*
* DON'T FORGET TO UPDATE THE BAUD RATE OF ANY
* UARTS YOU ARE USING AFTER CALLING THIS FUNCTION!
* ****************************************************************************/
void changeClockFreq(unsigned char mhz)
{
clock_frequency = (unsigned long)mhz*1000000;
// Temporarily disable interrupts level 1-6
disiOn();
// If the CPU is currently running on something other than the FRC
// switch to the FRC.
if (OSCCONbits.COSC != 0b000)
{
// Initiate clock switch to FRC Oscillator
__builtin_write_OSCCONH(0x00);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for clock switch to occur
while (OSCCONbits.COSC != 0b000);
}
// Conform the desired frequency if necessary
if (mhz < 15)
mhz = 15;
if (mhz > 140)
mhz = 140;
CLKDIVbits.PLLPRE = 0;
if (mhz <= 40) // 15-40 MHz
{
CLKDIVbits.PLLPOST = 3;
PLLFBD = (mhz*2)-2;
}
else if (mhz <= 80) // 40-80 MHz
{
CLKDIVbits.PLLPOST = 1;
PLLFBD = mhz-2;
}
else // 80-140 MHz
{
CLKDIVbits.PLLPOST = 0;
PLLFBD = (mhz/2)-2;
}
// Initiate clock switch to primary oscillator w/PLL
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for clock switch to occur
while (OSCCONbits.COSC != 0b011);
while (OSCCONbits.LOCK != 1);
// Re-enable interrupts level 1-6
disiOff();
}
void Inic_Oscilador(void)
{
// Configure Oscillator to operate the device at 40Mhz
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 8M*40/(2*2)=80Mhz for 8M input clock
// M=40 --> 80 Mhz Instrucción 25ns
// M=20 --> 40 Mhz Instrucción 50ns
// M=10 --> 20 Mhz Instrucción 100ns (
PLLFBD= 40-2; /* M=40 */
CLKDIVbits.PLLPOST=0; /* N1=2 */
CLKDIVbits.PLLPRE=0; /* N2=2 */
// OSCTUN=0; /* Tune FRC oscillator, if FRC is used */
// Disable Watch Dog Timer
RCONbits.SWDTEN=0;
// Clock switch to incorporate PLL
__builtin_write_OSCCONH(0x03); // Initiate Clock Switch to Primary
// Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONL(0x01); // Start clock switching
// funciones pre-compiladas: MPLAB C30 -DS51284G- apendice B
while (OSCCONbits.COSC != 0b011); // Wait for Clock switch to occur
// Wait for PLL to lock
while(OSCCONbits.LOCK!=1) {};
}
void init_OSC(void)
{
RCONbits.SWDTEN=0; //Disable WDT
CLKDIVbits.DOZE = 0b000; //Fcy divided by 1
CLKDIVbits.FRCDIV = 0b000; //FRC divided by 1
OSCTUNbits.TUN = 0b000000; //Center frequency FRC = 7,37Mhz
//Configure Oscillator to operate the device at 40MIPS
//Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
//Fosc= 7.37M*43/(2*2)=79.22Mhz for ~40MIPS input clock
//Fvco= Fin*M/N1=147.4Mhz
PLLFBD=41; //M=40
CLKDIVbits.PLLPOST=0; //N1=2
CLKDIVbits.PLLPRE=0; //N2=2
__builtin_write_OSCCONH(0x01); //Initiate Clock Switch to FRC with PLL (NOSC=0b001)
__builtin_write_OSCCONL(0x01); //Start clock switching
while(OSCCONbits.COSC!=0b001); //Wait for Clock switch to occur
while(OSCCONbits.LOCK!=1); //Wait for PLL to lock
//DAC rate max: 100Ksps
//The DAC clock must not exceed 100k*256=25,6Mhz
ACLKCONbits.SELACLK = 0; //FRC w/ Pll as Clock Source
ACLKCONbits.AOSCMD = 0; //Auxiliary Oscillator Disabled
ACLKCONbits.ASRCSEL = 0; //Auxiliary Oscillator is the Clock Source
ACLKCONbits.APSTSCLR = 0b111; //FRC divide by 1
}
return_value_t clock_init()
{
/*
* 70 MIPS:
* FOSC = Fin*(PLLDIV+2)/((PLLPRE+2)*2(PLLPOST+1))
* FOSC = 7.37MHz(74+2)/((0+2)*2(0+1)) = 140.03Mhz
* Fcy = FOSC/2
*/
PLLFBD = 74;
CLKDIVbits.PLLPRE = 0;
CLKDIVbits.PLLPOST = 0;
// Initiate Clock Switch to FRC oscillator with PLL (NOSC=0b001)
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur
while (OSCCONbits.COSC != 0b001);
while (OSCCONbits.LOCK!= 1);
clock_state.fcy = 70000000;
clock_state.init_return = RET_OK;
return clock_state.init_return;
}
void Setup(void) {
PinSetMode();
// setup internal clock for 72MHz/36MIPS
// 12 /2 = 6 *24 = 144 / 2=72
CLKDIVbits.PLLPRE = 0; // PLLPRE (N2) 0=/2c
CLKDIVbits.DOZE = 0;
PLLFBD = 22; // pll multiplier (M) = +2
CLKDIVbits.PLLPOST = 0; // PLLPOST (N1) 0=/2
// Initiate Clock Switch to Primary Oscillator with PLL (NOSC = 0b011)
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur
while (OSCCONbits.COSC != 0b011);
while (!OSCCONbits.LOCK); // wait for PLL ready
INTCON1bits.NSTDIS = 1; //no nesting of interrupts
timerOne();
initADC();
//timerTwo();
begin(receiveArray, sizeof (receiveArray), SAS_ADDRESS, false, Send_put, Receive_get, Receive_available, Receive_peek);
UART_init();
//UART1_init();
//begin(receiveArray1, sizeof (receiveArray1), SAS_ADDRESS, false, Send_put1, Receive_get1, Receive_available1, Receive_peek1);
}
void initADCDMA (void)
{
// Configure Oscillator to operate the device at 40Mhz
// Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
// Fosc= 8M*40/(2*2)=80Mhz for 8M input clock
PLLFBD=38; // M=40
CLKDIVbits.PLLPOST=0; // N1=2
CLKDIVbits.PLLPRE=0; // N2=2
OSCTUN=0; // Tune FRC oscillator, if FRC is used
// Disable Watch Dog Timer
RCONbits.SWDTEN=0;
// clock switching to incorporate PLL
__builtin_write_OSCCONH(0x03); // Initiate Clock Switch to Primary Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONL(OSCCON || 0x01); // Start clock switching
while (OSCCONbits.COSC != 0x03); // Wait for Clock switch to occur
while(OSCCONbits.LOCK!=1) {}; // Wait for PLL to lock
// Peripheral Initialisation
initDma0(); // Initialise the DMA controller to buffer ADC data in conversion order
initAdc1(); // Initialize the A/D converter to convert Channel 5 //Loop Endlessly - Execution is interrupt driven
//from this point on.
}
int main()
{
/// First step is to move over to the FRC w/ PLL clock from the default FRC clock.
// Set the clock to 79.84MHz.
PLLFBD = 63; // M = 65
CLKDIVbits.PLLPOST = 0; // N1 = 2
CLKDIVbits.PLLPRE = 1; // N2 = 3
// Initiate Clock Switch to FRM oscillator with PLL.
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur.
while (OSCCONbits.COSC != 1);
// And finally wait for the PLL to lock.
while (OSCCONbits.LOCK != 1);
// Initialize ADCs for reading voltage and temperature sensors
ImuNodeInit(F_OSC);
// Set up a timer at 100.0320Hz, where F_timer = F_CY / 256 / prescalar.
Timer2Init(SetTaskFlag, F_OSC / 2 / 256 / 100);
// Run system tasks when a timer interrupt has been triggered.
while (true) {
if (runTasks) {
Run100HzTasks();
runTasks = false;
}
RunContinuousTasks();
}
}
/*********************************************************************
* Function: void SYSTEM_Initialize( SYSTEM_STATE state )
*
* Overview: Initializes the system.
*
* PreCondition: None
*
* Input: SYSTEM_STATE - the state to initialize the system into
*
* Output: None
*
********************************************************************/
void SYSTEM_Initialize( SYSTEM_STATE state )
{
switch(state)
{
case SYSTEM_STATE_USB_START:
/*ANSELA = 0x0000;
ANSELB = 0x0000;
ANSELC = 0x0000;
ANSELD = 0x0000;
ANSELE = 0x0000;
ANSELG = 0x0000;*/
// Configure the device PLL to obtain 60 MIPS operation. The crystal
// frequency is 8MHz. Divide 8MHz by 2, multiply by 60 and divide by
// 2. This results in Fosc of 120MHz. The CPU clock frequency is
// Fcy = Fosc/2 = 60MHz. Wait for the Primary PLL to lock and then
// configure the auxilliary PLL to provide 48MHz needed for USB
// Operation.
PLLFBD = 58; /* M = 60 */
CLKDIVbits.PLLPOST = 0; /* N1 = 2 */
CLKDIVbits.PLLPRE = 0; /* N2 = 2 */
OSCTUN = 0;
/* Initiate Clock Switch to Primary
* Oscillator with PLL (NOSC= 0x3)*/
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(0x01);
while (OSCCONbits.COSC != 0x3);
// Configuring the auxiliary PLL, since the primary
// oscillator provides the source clock to the auxiliary
// PLL, the auxiliary oscillator is disabled. Note that
// the AUX PLL is enabled. The input 8MHz clock is divided
// by 2, multiplied by 24 and then divided by 2. Wait till
// the AUX PLL locks.
ACLKCON3 = 0x24C1;
ACLKDIV3 = 0x7;
ACLKCON3bits.ENAPLL = 1;
while(ACLKCON3bits.APLLCK != 1);
ADC_SetConfiguration(ADC_CONFIGURATION_DEFAULT);
ADC_ChannelEnable(ADC_CHANNEL_POTENTIOMETER);
LED_Enable(LED_USB_DEVICE_STATE);
LED_Enable(LED_USB_DEVICE_HID_CUSTOM);
BUTTON_Enable(BUTTON_USB_DEVICE_HID_CUSTOM);
break;
case SYSTEM_STATE_USB_SUSPEND:
break;
case SYSTEM_STATE_USB_RESUME:
break;
}
}
/*********************************************************************
* Function: void SYSTEM_Initialize( SYSTEM_STATE state )
*
* Overview: Initializes the system.
*
* PreCondition: None
*
* Input: SYSTEM_STATE - the state to initialize the system into
*
* Output: None
*
********************************************************************/
void SYSTEM_Initialize( SYSTEM_STATE state )
{
switch(state)
{
case SYSTEM_STATE_USB_HOST:
ANSELA = 0x0000;
ANSELB = 0x0000;
ANSELC = 0x0000;
ANSELD = 0x0000;
ANSELE = 0x0000;
ANSELG = 0x0000;
// Configure the device PLL to obtain 60 MIPS operation. The crystal
// frequency is 8MHz. Divide 8MHz by 2, multiply by 60 and divide by
// 2. This results in Fosc of 120MHz. The CPU clock frequency is
// Fcy = Fosc/2 = 60MHz. Wait for the Primary PLL to lock and then
// configure the auxilliary PLL to provide 48MHz needed for USB
// Operation.
PLLFBD = 58; /* M = 60 */
CLKDIVbits.PLLPOST = 0; /* N1 = 2 */
CLKDIVbits.PLLPRE = 0; /* N2 = 2 */
OSCTUN = 0;
/* Initiate Clock Switch to Primary
* Oscillator with PLL (NOSC= 0x3)*/
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(0x01);
while (OSCCONbits.COSC != 0x3);
// Configuring the auxiliary PLL, since the primary
// oscillator provides the source clock to the auxiliary
// PLL, the auxiliary oscillator is disabled. Note that
// the AUX PLL is enabled. The input 8MHz clock is divided
// by 2, multiplied by 24 and then divided by 2. Wait till
// the AUX PLL locks.
ACLKCON3 = 0x24C1;
ACLKDIV3 = 0x7;
ACLKCON3bits.ENAPLL = 1;
while(ACLKCON3bits.APLLCK != 1);
PRINT_SetConfiguration(PRINT_CONFIGURATION_LCD);
LED_Enable(LED_USB_HOST_HID_MOUSE_DEVICE_READY);
break;
case SYSTEM_STATE_USB_HOST_HID_MOUSE:
PRINT_SetConfiguration(PRINT_CONFIGURATION_LCD);
LCD_CursorEnable(true);
TIMER_SetConfiguration(TIMER_CONFIGURATION_1MS);
break;
}
}
void pllConfig(void) {
PLLFBD = 30; // M = 32
CLKDIVbits.PLLPOST = 0; // N1 = 2
CLKDIVbits.PLLPRE = 0; // N2 = 2
// Initiate Clock Switch to Primary Oscillator with PLL
__builtin_write_OSCCONH(3);
__builtin_write_OSCCONL(1);
// Wait for Clock switch to occur
while (OSCCONbits.COSC != 0b011);
}
void Clock_Init(void) {
// 80 MHz Oscillator Configure
PLLFBD = 0x0026; // M = 40
CLKDIV = 0x0000; // N1=2, N2=2
__builtin_write_OSCCONH(0x03); // Initiate Clock Switch to Primary Oscillator with PLL (NOSC=0x03)
__builtin_write_OSCCONL(OSCCON || 0x01); // Start clock switching
while(OSCCONbits.COSC != 0x03); // Wait for Clock switch to occur
while(OSCCONbits.LOCK!=1); // Wait for PLL to lock
}
int main()
{
/// First step is to move over to the FRC w/ PLL clock from the default FRC clock.
// Set the clock to 79.84MHz.
PLLFBD = 63; // M = 65
CLKDIVbits.PLLPOST = 0; // N1 = 2
CLKDIVbits.PLLPRE = 1; // N2 = 3
// Initiate Clock Switch to FRM oscillator with PLL.
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur.
while (OSCCONbits.COSC != 1);
// And finally wait for the PLL to lock.
while (OSCCONbits.LOCK != 1);
// Initialize the UART
Init();
CanMessage rxMsg;
char outStr[30];
while (1) {
// If we're active, listen for CAN messages and spit them out when they're found.
if (opMode == ACTIVE && Ecan1Receive(&rxMsg, NULL)) {
// Turn on the yellow LED whenever a CAN message is received
_LATA4 = 1;
int bytesToSend;
if ((bytesToSend = MessageToString(outStr, sizeof(outStr), &rxMsg))) {
// We send 1 less than the output, because that last part is just
// a NUL character.
Uart1WriteData(outStr, bytesToSend - 1);
}
_LATA4 = 0;
}
// Regardless of run state, listen for incoming commands
uint8_t u1RxData;
if (Uart1ReadByte(&u1RxData)) {
int commandResponse = ProcessIncomingCommandStream(u1RxData);
// Output a CR if the command was successfully executed
if (commandResponse > 0) {
Uart1WriteByte('\r');
}
// Otherwise output a BEL if there was an error.
else if (commandResponse < 0) {
Uart1WriteByte('\b');
}
// The 0 value returned doesn't warrant an output as it's a command sequence in progress.
}
}
}
void init_osc() {
// Init de la PLL
CLKDIVbits.PLLPRE = 0; // (FRC) /2
PLLFBD = 41; // (FRC/2) *43
CLKDIVbits.PLLPOST = 0; // (FRC/2*43) /2
__builtin_write_OSCCONH((OSCCONH | 1 )& 0xF9); // Choix de l'horloge FRC avec PLL
__builtin_write_OSCCONL(OSCCONL | 1); // Changement d'horloge
//while (!OSCCONbits.LOCK); // Attend le bloquage de la PLL (debug)
while (OSCCONbits.OSWEN); // Attend le changement
}
void PLLConfig(void)
{
PLLFBD = 78; // M = 80
CLKDIVbits.PLLPOST = 0; // N2 = 2
CLKDIVbits.PLLPRE = 3; // N1 = 5
// Initiate Clock Switch to Internal FRC with PLL (NOSC = 0b001)
__builtin_write_OSCCONH(0x01); // Selects the new Oscillator,FRCPLL
__builtin_write_OSCCONL(0x01); // Request Osc switch to FRCPLL
while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur
while(OSCCONbits.LOCK!=1); // Wait for PLL to lock
}
int main(void) {
/* Init Clock */
PLLFBD = 126;
CLKDIVbits.PLLPOST = 0;
CLKDIVbits.PLLPRE = 1;
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(OSCCON | 0x01);
while (OSCCONbits.COSC != 3) ;
while (OSCCONbits.LOCK != 1) ;
tx_fifo.head=0;
tx_fifo.tail=0;
rx_fifo.head=0;
rx_fifo.tail=0;
/* Init PORT I/O */
init_io();
init_pps();
init_uart();
init_can();
while (true) {
counter++;
counter_can++;
fifo_putchar(&tx_fifo);
if (can_test_receive())
print_rom_fifo("received CAN packet\r\n", &tx_fifo);
if (counter_can == 30000) {
can_test_send();
counter_can = 0;
}
if (counter == 50000) {
print_rom_fifo("Hello dsPIC33 !\r\n", &tx_fifo);
//print_debug_fifo(&tx_fifo);
// ClrWdt();
counter = 0;
}
__delay_us(10);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
__builtin_btg((unsigned int *)&LATA, 0);
}
}
void useFRCPLLClock(){
// Configure PLL prescaler, PLL postscaler, PLL divisor
PLLFBD = 41; // M = 43
CLKDIVbits.PLLPOST=0; // N2 = 2
CLKDIVbits.PLLPRE=0; // N1 = 2
// Initiate Clock Switch to Internal FRC with PLL (NOSC = 0b001)
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(0x01);
// Wait for Clock switch to occur
while (OSCCONbits.COSC != 0b001);
// Wait for PLL to lock
while(OSCCONbits.LOCK != 1) {};
}
void osc_switch(_OSCILATOR osc) {
SYSHANDLE prevState = high_priority_enter();
// Initiate Clock Switch
__builtin_write_OSCCONH((unsigned char) osc);
// Switch (first bit in OSCCONL)
osccon_set_bit(1, 0);
// Wait for Clock switch to occur
while (OSCCONbits.COSC != (unsigned char) osc);
high_priority_exit(prevState);
}
// Main clk freq after PLL = 8291500 Hz
int init_pll()
{
PLLFBD = M - 2;
CLKDIVbits.PLLPOST = N1 - 2;
CLKDIVbits.PLLPRE = N2/2 - 1;
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(0x01);
// Wait for Clock switch to occur
while(OSCCONbits.COSC != 0b001);
while(OSCCONbits.LOCK!=1) {}; // Wait for PLL to lock
return 0;
}
void ClockInit(void)
{
PLLFBD = 242; // M = 50 MIPS
CLKDIVbits.PLLPOST = 0;
CLKDIVbits.PLLPRE = 7;
OSCTUN = 0;
RCONbits.SWDTEN = 0;
__builtin_write_OSCCONH(0x01); // Initiate Clock Switch to Primary (3?)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur
while (OSCCONbits.LOCK != 1) {
};
}
/* The initialize function configures the PLL to set the internal clock
* frequency. It also configures the digital IO and calls the initialization
* functions for each of the modules. A light sequence signals the end of
* initialization.
*/
void initialize(void){
/* Configure Phase Lock Loop for the system clock reference at 40MHz */
// Fosc (Clock frequency) is set at 80MHz
// Fin is 7.37 MHz from internal FRC oscillator
// FPLLI = Fin/N1 = 3.685 MHz
CLKDIVbits.PLLPRE = 0; // N1 = 2
// FVCO = FPLLI*M1 = 162.14MHz
PLLFBDbits.PLLDIV = 42; // M = 44
// FPLLO = FVCO/N2 = 81.07 MHz
// FOSC ~= 80MHz, FCY ~= 40MHz
CLKDIVbits.PLLPOST = 0; // N2 = 2
/* Initiate Clock Switch */
//The __builtin macro handles unlocking the OSCCON register
__builtin_write_OSCCONH(1); //New oscillator is FRC with PLL
__builtin_write_OSCCONL(OSCCON | 0x01); //Enable clock switch
while (OSCCONbits.COSC!= 1); //Wait for FRC with PLL to be clock source
while (OSCCONbits.LOCK!= 1); //Wait for PLL to lock
/* Configure IO*/
TRISDbits.TRISD10 = 1; //USER input
//LED outputs
ANSELBbits.ANSB13 = 0; //Disable Analog on B13
TRISBbits.TRISB13 = 0; //LED1
ANSELBbits.ANSB12 = 0; //Disable Analog on B12
TRISBbits.TRISB12 = 0; //LED2
TRISDbits.TRISD11 = 0; //LED3
TRISDbits.TRISD0 = 0; //LED4
//Magnet Control
TRISBbits.TRISB14 = 0; //Top Magnet
//Store bits indicating reason for reset
resetStat = RCON;
//Clear reset buffer so next reset reading is correct
RCON = 0;
/* Initialize peripherals*/
initialize_PWM();
initialize_CN();
initialize_ADC();
initialize_QEI();
initialize_UART();
initialize_UART2();
//initialize_I2C_Master();
lights();
__delay32(10000000);
//initialize_MPU();
initialize_encoder_values(1600,1700,1800);
}
void hw_init(void)
{
/* LED */
LED_DIR = 0;
LED = 0;
/* make all ports digital */
ANSELA = 0;
ANSELB = 0;
ANSELC = 0;
/* for debug */
TRISBbits.TRISB4 = 0;
LATBbits.LATB4 = 0;
#ifndef WITH_BOOTLOADER
/* oscillator config */
/* Fosc = 140MHz (70MIPS) */
/* Fsys = 280MHz */
CLKDIVbits.PLLPRE = 0;
CLKDIVbits.PLLPOST = 0;
PLLFBDbits.PLLDIV = 74;
/* switch clock to FRC oscillator with PLL */
__builtin_write_OSCCONH(1);
__builtin_write_OSCCONL(OSCCON | 1);
/* wait for clock switch to complete */
while (OSCCONbits.OSWEN == 1);
/* wait for PLL lock */
while (OSCCONbits.LOCK != 1);
#endif
#ifdef DEBUG_INIT
printf("AlceOSD\r\n");
if (RCONbits.WDTO)
printf("watchdog reset\r\n");
if (RCONbits.EXTR)
printf("external reset\r\n");
if (RCONbits.SWR)
printf("software reset\r\n");
if (RCONbits.IOPUWR)
printf("ill opcode / uninit W reset\r\n");
if (RCONbits.WDTO)
printf("trap conflict reset\r\n");
#endif
LED = 1;
}
void ConfigureOscillator(void) {
PLLFBD = 30; // M=32 //Old configuration: PLLFBD=29 - M=31
CLKDIVbits.PLLPOST = 0; // N1=2
CLKDIVbits.PLLPRE = 0; // N2=2
// Disable Watch Dog Timer
RCONbits.SWDTEN = 0;
// Clock switching to incorporate PLL
// Initiate Clock Switch to Primary
__builtin_write_OSCCONH(0x03); // Oscillator with PLL (NOSC=0b011)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b011); // Wait for Clock switch to occur
while (OSCCONbits.LOCK != 1) {
}; // Wait for PLL to lock
}
/*********************************************************************
* Function: void SYSTEM_Initialize( SYSTEM_STATE state )
*
* Overview: Initializes the system.
*
* PreCondition: None
*
* Input: SYSTEM_STATE - the state to initialize the system into
*
* Output: None
*
********************************************************************/
void SYSTEM_Initialize( SYSTEM_STATE state )
{
switch(state)
{
case SYSTEM_STATE_USB_START:
//Make sure that the general purpose output driver multiplexed with
//the VBUS pin is always consistently configured to be tri-stated in
//USB applications, so as to avoid any possible contention with the host.
//(ex: maintain TRISFbits.TRISF7 = 1 at all times).
TRISFbits.TRISF7 = 1;
//Configure clock settings to be compatible with USB operation.
//This could involve doing nothing (ex: if the config bit settings
//already result in a USB compatible clock frequency at bootup), or,
//could involve clock switching and/or turning on the PLL and/or turning
//on the active clock tuning feature.
#if defined(USB_RUN_FROM_EXPLORER_16_8MHZ_CRYSTAL)
//Don't need to do anything, with the default config bit settings for this
//oscillator setting, since the settings will already be USB compatible.
#else
//Assume USB_RUN_FROM_FRCPLL_WITH_ACTIVE_CLOCK_TUNING is selected instead.
CLKDIV = 0x3120; //Set FRC to 4MHz output mode, and CPUDIV to 1:1 (which is a USB compatible setting)
__builtin_write_OSCCONH(0x01); //0x01 = FRCPLL with postscalar
__builtin_write_OSCCONL(OSCCON | 0x0001); //Set the OSWEN bit, to initiate clock switching operation.
//Wait for PLL lock
while(OSCCONbits.LOCK == 0);
//Turn on the active clock tuning for USB operation
OSCTUN = 0x9000; //Enable active clock tuning from USB host reference
//The oscillator settings should now be USB compatible.
#endif
//Configure other USB or application related resources.
LED_Enable(LED_USB_DEVICE_STATE);
LED_Enable(LED_USB_DEVICE_HID_KEYBOARD_CAPS_LOCK);
BUTTON_Enable(BUTTON_USB_DEVICE_HID_KEYBOARD_KEY);
BUTTON_Enable(BUTTON_USB_DEVICE_REMOTE_WAKEUP);
break;
case SYSTEM_STATE_USB_SUSPEND:
break;
case SYSTEM_STATE_USB_RESUME:
break;
default:
break;
}
}
void clock_init()
{
PLLFBD = 41;
CLKDIVbits.PLLPOST = 0;
CLKDIVbits.PLLPRE = 0;
OSCTUN = 0;
RCONbits.SWDTEN = 0;
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(0x01);
while (OSCCONbits.COSC != 0b001) {}
while (OSCCONbits.LOCK != 1) {}
}
void InitClock() {
PLLFBD = 38; // M = 40
CLKDIVbits.PLLPOST = 0; // N1 = 2
CLKDIVbits.PLLPRE = 0; // N2 = 2
OSCTUN = 0;
RCONbits.SWDTEN = 0;
// Clock switch to incorporate PLL
__builtin_write_OSCCONH(0x01); // Initiate Clock Switch to
// FRC with PLL (NOSC=0b001)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur
while(OSCCONbits.LOCK != 1) {};
}
void ConfigureOscillator(void)
{
/* Disable Watch Dog Timer */
RCONbits.SWDTEN = 0;
/* When clock switch occurs switch to Pri Osc controlled by FPR<4:0> */
__builtin_write_OSCCONH(0x03); /* Set OSCCONH for clock switch */
__builtin_write_OSCCONL(0x01); /* Start clock switching */
/* Wait for Clock switch to occur */
//while(OSCCONbits.COSC != 0b011);
/* Wait for PLL to lock, if PLL is used */
while(OSCCONbits.LOCK != 1);
}
void initApp( void )
{
// Description: Configuring internal oscillator with PLL (7.37 MHz -> 80 MHz )
PLLFBD = 41; // M = 43
CLKDIVbits.PLLPOST=0; // N1 = 2
CLKDIVbits.PLLPRE=0; // N2 = 2
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(0x01);
while (OSCCONbits.COSC != 0b001);
while (OSCCONbits.LOCK != 1);
AD1PCFGL = 0xFFFF; // all digital IO
TRISA = 0xFF; // Set all RA* as inputs
TRISAbits.TRISA0 = 0; // LED output
TRISB = 0xFF; // Set all RB* as inputs
}
static void sys_ConfigClock()
{
/* Clock setup on " dsPIC33F/PC24 Family Reference Manual : 70186E Section 7. Oscillator " */
/* Configure PLL prescaler, PLL post scaller, PLL divisor
* Fosc = Fin * ( M / (N1*N2) )
* N1 = PLLPRE + 2
* N2 = 2 * (PLLPOST + 1)
* M = PLLDIV + 2
*
* Fin = 7372800 [Hz]
* PLLPRE = 4
* PLLPOST = 0
* PLLDIV = 128
* N1 = 6
* N2 = 2
* M = 130
*
* Fosc = 7372800 * ( 130 / (6*2) )
* = 79872000
*
* Fcy = Fosc / 2 = 39936000 [Hz]
*/
// PLLFBD: PLL Feedback Divisor Resgister
PLLFBD = 128; /* PLLDIV<8:0> = 128 M, PLL Multiplier */
// CLKDIV: Clock Divisor Register
CLKDIV =
(0U << 6) | /* PLLPOST<7:6> = 00 Output divided by 2
N2, PLL Postscaller */
(4U << 0); /* PLLPRE(4:0> = 4 Input divided by 6
N1, PLL Prescaler */
/* Initiate clock switch to Primary Oscillator with PLL (NOSc = 0b011) */
__builtin_write_OSCCONH(0x03);
__builtin_write_OSCCONL(0x01);
#if !defined(_MPLAB_SIM)
/* Wait fo clock switch to occur */
while(OSCCONbits.COSC != 0x03);
/* Wait for PLL to lock */
while(OSCCONbits.LOCK != 1);
#endif
}
static void osc_setup(void)
{
/* fast rc oscillator */
PLLFBD = 41;
CLKDIVbits.PLLPOST = 0;
CLKDIVbits.PLLPRE = 0;
OSCTUN = 0;
RCONbits.SWDTEN = 0;
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(0x01);
while (OSCCONbits.COSC != 1) ;
while (OSCCONbits.LOCK != 1) ;
}
