void plat_cpu_reset_late(void)
{
static uint32_t cntfrq;
vaddr_t addr;
if (!get_core_pos()) {
/* read cnt freq */
cntfrq = read_cntfrq();
#if defined(CFG_BOOT_SECONDARY_REQUEST)
/* set secondary entry address */
write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR),
DCFG_BASE + DCFG_SCRATCHRW1);
/* release secondary cores */
write32(__compiler_bswap32(0x1 << 1), /* cpu1 */
DCFG_BASE + DCFG_CCSR_BRR);
dsb();
sev();
#endif
/* configure CSU */
/* first grant all peripherals */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
write32(__compiler_bswap32(CSU_ACCESS_ALL), addr);
/* restrict key preipherals from NS */
write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY),
CSU_BASE + CSU_CSL30);
write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY),
CSU_BASE + CSU_CSL37);
/* lock the settings */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
write32(read32(addr) |
__compiler_bswap32(CSU_SETTING_LOCK),
addr);
} else {
/* program the cntfrq, the cntfrq is banked for each core */
write_cntfrq(cntfrq);
}
}
void plat_cpu_reset_late(void)
{
vaddr_t addr;
if (!get_core_pos()) {
#if defined(CFG_BOOT_SECONDARY_REQUEST)
/* set secondary entry address */
io_write32(DCFG_BASE + DCFG_SCRATCHRW1,
__compiler_bswap32(TEE_LOAD_ADDR));
/* release secondary cores */
io_write32(DCFG_BASE + DCFG_CCSR_BRR /* cpu1 */,
__compiler_bswap32(0x1 << 1));
dsb();
sev();
#endif
/* configure CSU */
/* first grant all peripherals */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
io_write32(addr, __compiler_bswap32(CSU_ACCESS_ALL));
/* restrict key preipherals from NS */
io_write32(CSU_BASE + CSU_CSL30,
__compiler_bswap32(CSU_ACCESS_SEC_ONLY));
io_write32(CSU_BASE + CSU_CSL37,
__compiler_bswap32(CSU_ACCESS_SEC_ONLY));
/* lock the settings */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
io_setbits32(addr,
__compiler_bswap32(CSU_SETTING_LOCK));
}
}
