/** \brief Test case: TC_CoreFunc_APSR \details - Check if __get_APSR intrinsic is available - Check if __get_xPSR intrinsic is available - Check negative, zero and overflow flags */ void TC_CoreFunc_APSR (void) { uint32_t result; //lint -esym(838, Rm) unused values //lint -esym(438, Rm) unused values // Check negative flag int32_t Rm = 5; int32_t Rn = 7; SUBS(Rm, Rm, Rn); result = __get_APSR(); ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk); Rm = 5; Rn = 7; SUBS(Rm, Rm, Rn); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk); // Check zero and compare flag Rm = 5; SUBS(Rm, Rm, Rm); result = __get_APSR(); ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk); ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); Rm = 5; SUBS(Rm, Rm, Rm); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk); ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk); // Check overflow flag Rm = 5; Rn = INT32_MAX; ADDS(Rm, Rm, Rn); result = __get_APSR(); ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk); Rm = 5; Rn = INT32_MAX; ADDS(Rm, Rm, Rn); result = __get_xPSR(); ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk); }
/** \brief Test case: TC_CoreSimd_ParSel \details - Check Parallel selection: __SEL */ void TC_CoreSimd_ParSel (void) { #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) ) volatile uint32_t res_u32; volatile int32_t op1_s32, op2_s32; volatile int32_t res_s32; APSR_Type apsr; xPSR_Type xpsr; /* --- __SEL Test ---------------------------------------------- */ op1_s32 = 0x33221100; op2_s32 = 0x77665544; res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */ ASSERT_TRUE( res_s32 == 0x77665544); res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */ ASSERT_TRUE(res_s32 == 0x77665500); res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */ res_u32 = __get_APSR(); apsr.w = __get_APSR(); ASSERT_TRUE( (res_u32 == apsr.w) ); xpsr.w = __get_xPSR(); ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) ); res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */ ASSERT_TRUE(res_s32 == 0x77661144); #endif }