Exemplo n.º 1
0
static void spm_sodi_pre_process(void)
{
    /* set PMIC WRAP table for deepidle power control */
    mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);	

    vsram_vosel_on_lb = __spm_dpidle_sodi_set_pmic_setting();
}
static void spm_sodi_pre_process(void)
{
    /* set PMIC WRAP table for deepidle power control */
    mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
/* [521562] merge ALPS02212031(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P82) patch by liming.zhu at 20150818 bigen*/
    vsram_vosel_on_lb = __spm_dpidle_sodi_set_pmic_setting();
	/* [521562] merge ALPS02212031(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P82) patch by liming.zhu at 20150818 end*/
}
static void spm_dpidle_pre_process(void)
{
/*  //TODO
    spm_i2c_control(I2C_CHANNEL, 1);//D1,D2 no ext bulk
    g_bus_ctrl=spm_read(0xF0001070);
    spm_write(0xF0001070 , g_bus_ctrl | (1 << 21)); //bus dcm disable
    g_sys_ck_sel = spm_read(0xF0001108);
    //spm_write(0xF0001108 , g_sys_ck_sel &~ (1<<1) );
    spm_write(0xF0001108 , 0x0);
    spm_write(0xF0000204 , spm_read(0xF0000204) | (1 << 0));  // BUS 26MHz enable 
*/
    /* set PMIC WRAP table for deepidle power control */
    mt_cpufreq_set_pmic_phase(PMIC_WRAP_PHASE_DEEPIDLE);
	/* [521562] merge ALPS02212031(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P82) patch by liming.zhu at 20150818 bigen*/
	vsram_vosel_on_lb = __spm_dpidle_sodi_set_pmic_setting();
	/* [521562] merge ALPS02212031(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P82) patch by liming.zhu at 20150818 end*/
}