/* Requirements : HL_SR508 */
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
*
* Errata Description:
* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
* Workaround:
* Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
if (DEVICE_ID_REV == 0x802AAD05U)
{
_esmCcmErrorsClear_();
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Workaround for Errata CORTEXR4 66 */
_errata_CORTEXR4_66_();
/* Workaround for Errata CORTEXR4 57 */
_errata_CORTEXR4_57_();
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
/* check for power-on reset condition */
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* USER CODE BEGIN (13) */
/* USER CODE END */
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
/*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->SR1[2]) != 0U)
{
/* USER CODE BEGIN (24) */
/* USER CODE END */
/*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
for(;;)
{
}/* Wait */
/* USER CODE BEGIN (25) */
/* USER CODE END */
}
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* Workaround for Errata PBIST#4 */
errata_PBIST_4();
/* Run a diagnostic check on the memory self-test controller.
* This function chooses a RAM test algorithm and runs it on an on-chip ROM.
* The memory self-test is expected to fail. The function ensures that the PBIST controller
* is capable of detecting and indicating a memory self-test failure.
*/
pbistSelfCheck();
/* Run PBIST on STC ROM */
pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for STC ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
/* Check if PBIST on STC ROM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* PBIST and STC ROM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
pbistFail();
}
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* Run PBIST on PBIST ROM */
pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
/* Wait for PBIST for PBIST ROM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
/* Check if PBIST ROM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* PBIST and STC ROM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
pbistFail();
}
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* USER CODE BEGIN (31) */
/* USER CODE END */
/* Disable RAM ECC before doing PBIST for Main RAM */
_coreDisableRamEcc_();
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
/* USER CODE BEGIN (33) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
/* USER CODE BEGIN (34) */
/* USER CODE END */
pbistFail();
/* USER CODE BEGIN (35) */
/* USER CODE END */
}
/* USER CODE BEGIN (36) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (37) */
/* USER CODE END */
/* Initialize CPU RAM.
* This function uses the system module's hardware for auto-initialization of memories and their
* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
* Hence the value 0x1 passed to the function.
* This function will initialize the entire CPU RAM and the corresponding ECC locations.
*/
memoryInit(0x1U);
/* USER CODE BEGIN (38) */
/* USER CODE END */
/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
_coreEnableRamEcc_();
/* USER CODE BEGIN (39) */
/* USER CODE END */
/* Start PBIST on all dual-port memories */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories.
PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
pbistRun( (uint32)0x00000000U /* EMAC RAM */
| (uint32)0x00000000U /* USB RAM */
| (uint32)0x00000800U /* DMA RAM */
| (uint32)0x00000200U /* VIM RAM */
| (uint32)0x00000040U /* MIBSPI1 RAM */
| (uint32)0x00000080U /* MIBSPI3 RAM */
| (uint32)0x00000100U /* MIBSPI5 RAM */
| (uint32)0x00000004U /* CAN1 RAM */
| (uint32)0x00000008U /* CAN2 RAM */
| (uint32)0x00000010U /* CAN3 RAM */
| (uint32)0x00000400U /* ADC1 RAM */
| (uint32)0x00020000U /* ADC2 RAM */
| (uint32)0x00001000U /* HET1 RAM */
| (uint32)0x00040000U /* HET2 RAM */
| (uint32)0x00002000U /* HTU1 RAM */
| (uint32)0x00080000U /* HTU2 RAM */
| (uint32)0x00004000U /* RTP RAM */
| (uint32)0x00008000U /* FRAY RAM */
,(uint32) PBIST_March13N_DP);
/* USER CODE BEGIN (40) */
/* USER CODE END */
/* Test the CPU ECC mechanism for RAM accesses.
* The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
* in the ECC causes a data abort exception. The data abort handler is written to look for
* deliberately caused exception and to return the code execution to the instruction
* following the one that caused the abort.
*/
checkRAMECC();
/* USER CODE BEGIN (41) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
/* USER CODE BEGIN (44) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* USER CODE BEGIN (45) */
/* USER CODE END */
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
/* USER CODE BEGIN (46) */
/* USER CODE END */
pbistFail();
/* USER CODE BEGIN (47) */
/* USER CODE END */
}
/* USER CODE BEGIN (48) */
/* USER CODE END */
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
/* USER CODE BEGIN (55) */
/* USER CODE END */
/* Release the MibSPI1 modules from local reset.
* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
*/
mibspiREG1->GCR0 = 0x1U;
/* Release the MibSPI3 modules from local reset.
* This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
*/
mibspiREG3->GCR0 = 0x1U;
/* Release the MibSPI5 modules from local reset.
* This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
*/
mibspiREG5->GCR0 = 0x1U;
/* USER CODE BEGIN (56) */
/* USER CODE END */
/* Enable parity on selected RAMs */
enableParity();
/* Initialize all on-chip SRAMs except for MibSPIx RAMs
* The MibSPIx modules have their own auto-initialization mechanism which is triggered
* as soon as the modules are brought out of local reset.
*/
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
*/
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
memoryInit( (uint32)((uint32)1U << 1U) /* DMA RAM */
| (uint32)((uint32)1U << 2U) /* VIM RAM */
| (uint32)((uint32)1U << 5U) /* CAN1 RAM */
| (uint32)((uint32)1U << 6U) /* CAN2 RAM */
| (uint32)((uint32)1U << 10U) /* CAN3 RAM */
| (uint32)((uint32)1U << 8U) /* ADC1 RAM */
| (uint32)((uint32)1U << 14U) /* ADC2 RAM */
| (uint32)((uint32)1U << 3U) /* HET1 RAM */
| (uint32)((uint32)1U << 4U) /* HTU1 RAM */
| (uint32)((uint32)1U << 15U) /* HET2 RAM */
| (uint32)((uint32)1U << 16U) /* HTU2 RAM */
);
/* Disable parity */
disableParity();
/* Test the parity protection mechanism for peripheral RAMs
NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
/* USER CODE BEGIN (57) */
/* USER CODE END */
het1ParityCheck();
/* USER CODE BEGIN (58) */
/* USER CODE END */
htu1ParityCheck();
/* USER CODE BEGIN (59) */
/* USER CODE END */
het2ParityCheck();
/* USER CODE BEGIN (60) */
/* USER CODE END */
htu2ParityCheck();
/* USER CODE BEGIN (61) */
/* USER CODE END */
adc1ParityCheck();
/* USER CODE BEGIN (62) */
/* USER CODE END */
adc2ParityCheck();
/* USER CODE BEGIN (63) */
/* USER CODE END */
can1ParityCheck();
/* USER CODE BEGIN (64) */
/* USER CODE END */
can2ParityCheck();
/* USER CODE BEGIN (65) */
/* USER CODE END */
can3ParityCheck();
/* USER CODE BEGIN (66) */
/* USER CODE END */
vimParityCheck();
/* USER CODE BEGIN (67) */
/* USER CODE END */
dmaParityCheck();
/* USER CODE BEGIN (68) */
/* USER CODE END */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI1 RAM to complete initialization */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI3 RAM to complete initialization */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
{
}/* Wait */
/* wait for MibSPI5 RAM to complete initialization */
/* USER CODE BEGIN (69) */
/* USER CODE END */
mibspi1ParityCheck();
/* USER CODE BEGIN (70) */
/* USER CODE END */
mibspi3ParityCheck();
/* USER CODE BEGIN (71) */
/* USER CODE END */
mibspi5ParityCheck();
/* USER CODE BEGIN (72) */
/* USER CODE END */
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* USER CODE BEGIN (73) */
/* USER CODE END */
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (74) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
/* initialize copy table */
__TI_auto_init();
/* USER CODE BEGIN (75) */
/* USER CODE END */
/* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
main();
/* USER CODE BEGIN (76) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
exit(0);
/* USER CODE BEGIN (77) */
/* USER CODE END */
}
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
switch(getResetSource())
{
case POWERON_RESET:
case DEBUG_RESET:
case EXT_RESET:
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize L2RAM to avoid ECC errors right after power on */
_memInit_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (9) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (10) */
/* USER CODE END */
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case. */
if ((esmREG->SR1[2]) != 0U)
{
esmGroup3Notification(esmREG,esmREG->SR1[2]);
}
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* Configure system response to error conditions signaled to the ESM group1 */
/* This function can be configured from the ESM tab of HALCoGen */
esmInit();
/* USER CODE BEGIN (13) */
/* USER CODE END */
break;
case OSC_FAILURE_RESET:
/* USER CODE BEGIN (14) */
/* USER CODE END */
break;
case WATCHDOG_RESET:
/* USER CODE BEGIN (15) */
/* USER CODE END */
break;
case CPU0_RESET:
case CPU1_RESET:
/* USER CODE BEGIN (16) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (18) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (19) */
/* USER CODE END */
break;
case SW_RESET:
/* USER CODE BEGIN (20) */
/* USER CODE END */
break;
default:
/* USER CODE BEGIN (21) */
/* USER CODE END */
break;
}
/* USER CODE BEGIN (22) */
/* USER CODE END */
_mpuInit_();
/* USER CODE BEGIN (23) */
/* USER CODE END */
_cacheEnable_();
/* USER CODE BEGIN (24) */
/* USER CODE END */
/* USER CODE BEGIN (25) */
/* USER CODE END */
/* initialize global variable and constructors */
__TI_auto_init();
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* call the application */
/*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
/*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
/*SAFETYMCUSW 60 D MR:8.8 <APPROVED> "Startup code(Declaration for main in library;Only doing an extern for the same)" */
main();
/* USER CODE BEGIN (27) */
/* USER CODE END */
/*SAFETYMCUSW 122 S MR:20.11 <APPROVED> "Startup code(exit and abort need to be present)" */
exit(0);
/* USER CODE BEGIN (28) */
/* USER CODE END */
}
void _c_int00(void)
{
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Initialize Core Registers to avoid CCM Error */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
*
* Errata Description:
* The Core Compare Module(CCM-R4) may cause nERROR to be asserted after a cold power-on
* Workaround:
* Clear ESM Group2 Channel 2 error in ESMSR2 and Compare error in CCMSR register */
if (DEVICE_ID_REV == 0x802AAD05U)
{
_esmCcmErrorsClear_();
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset.
*/
/* check for power-on reset condition */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* USER CODE BEGIN (13) */
/* USER CODE END */
_errata_CORTEXR4_66_();
/* USER CODE BEGIN (14) */
/* USER CODE END */
_errata_CORTEXR4_57_();
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->ESTATUS1[2]) != 0U)
{
/* for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below */
/* USER CODE BEGIN (24) */
/* USER CODE END */
for(;;)
{
}/* Wait */
/* USER CODE BEGIN (25) */
/* USER CODE END */
}
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* Run a diagnostic check on the memory self-test controller.
* This function chooses a RAM test algorithm and runs it on an on-chip ROM.
* The memory self-test is expected to fail. The function ensures that the PBIST controller
* is capable of detecting and indicating a memory self-test failure.
*/
pbistSelfCheck();
/* USER CODE BEGIN (31) */
/* USER CODE END */
/* Run PBIST on CPU RAM.
* The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
* The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
* device datasheet.
*/
pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);
/* USER CODE BEGIN (32) */
/* USER CODE END */
/* Wait for PBIST for CPU RAM to be completed */
while((!pbistIsTestCompleted()) == TRUE)
{
}/* Wait */
/* USER CODE BEGIN (33) */
/* USER CODE END */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
if(pbistPortTestStatus((uint32)PBIST_PORT0) != TRUE)
{
memoryPort0TestFailNotification((uint32)((pbistREG->RAMT & 0xFF000000U) >> 24U), (uint32)((pbistREG->RAMT & 0x00FF0000U) >> 16U), (uint32)pbistREG->FSRA0, (uint32)pbistREG->FSRDL0);
}
else if(pbistPortTestStatus((uint32)PBIST_PORT1) != TRUE)
void _c_int00()
{
register uint32_t temp;
/* USER CODE BEGIN (5) */
/* USER CODE END */
/* Enable VFP Unit */
_coreEnableVfp_();
/* Initialize Core Registers */
_coreInitRegisters_();
/* USER CODE BEGIN (6) */
/* USER CODE END */
/* read the system exception status register */
temp = systemREG1->SYSESR;
/* USER CODE BEGIN (7) */
/* USER CODE END */
/* check for power-on reset condition */
if (temp & 0x8000)
{
/* clear all reset status flags */
systemREG1->SYSESR = 0xFFFF;
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
else if (temp & 0x4000)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (9) */
/* USER CODE END */
}
else if (temp & 0x2000)
{
/* Reset caused due to windowed watchdog violation.
Add user code here to handle watchdog violation */
/* USER CODE BEGIN (10) */
/* USER CODE END */
}
else if (temp & 0x20)
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register.
Add user code to handle CPU reset:
check for selftest completion without any error and continue start-up. */
/* USER CODE BEGIN (11) */
/* USER CODE END */
}
else if (temp & 0x10)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (13) */
/* USER CODE END */
}
/* Initialize Stack Pointers */
_coreInitStackPointer_();
/* Enable IRQ offset via Vic controller */
_coreEnableIrqVicOffset_();
/* Initialize System */
systemInit();
/* Initialize memory */
// _memoryInit_();
/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
// _coreEnableEventBusExport_();
/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
// _coreEnableRamEcc_();
/* Initialize VIM table */
{
uint32_t i;
for (i = 0; i < 90U; i++)
{
vimRAM->ISR[i] = s_vim_init[i];
}
}
/* set IRQ/FIQ priorities */
vimREG->FIRQPR0 = SYS_FIQ
| (SYS_FIQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U)
| (SYS_IRQ << 31U);
vimREG->FIRQPR1 = SYS_IRQ
| (SYS_IRQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U)
| (SYS_IRQ << 26U)
| (SYS_IRQ << 27U)
| (SYS_IRQ << 28U)
| (SYS_IRQ << 29U)
| (SYS_IRQ << 30U)
| (SYS_IRQ << 31U);
vimREG->FIRQPR2 = SYS_IRQ
| (SYS_IRQ << 1U)
| (SYS_IRQ << 2U)
| (SYS_IRQ << 3U)
| (SYS_IRQ << 4U)
| (SYS_IRQ << 5U)
| (SYS_IRQ << 6U)
| (SYS_IRQ << 7U)
| (SYS_IRQ << 8U)
| (SYS_IRQ << 9U)
| (SYS_IRQ << 10U)
| (SYS_IRQ << 11U)
| (SYS_IRQ << 12U)
| (SYS_IRQ << 13U)
| (SYS_IRQ << 14U)
| (SYS_IRQ << 15U)
| (SYS_IRQ << 16U)
| (SYS_IRQ << 17U)
| (SYS_IRQ << 18U)
| (SYS_IRQ << 19U)
| (SYS_IRQ << 20U)
| (SYS_IRQ << 21U)
| (SYS_IRQ << 22U)
| (SYS_IRQ << 23U)
| (SYS_IRQ << 24U)
| (SYS_IRQ << 25U);
/* enable interrupts */
vimREG->REQMASKSET0 = 1U
| (1U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U)
| (0U << 26U)
| (0U << 27U)
| (0U << 28U)
| (0U << 29U)
| (0U << 30U)
| (0U << 31U);
vimREG->REQMASKSET1 = 0U
| (0U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U)
| (0U << 26U)
| (0U << 27U)
| (0U << 28U)
| (0U << 29U)
| (0U << 30U)
| (0U << 31U);
vimREG->REQMASKSET2 = 0U
| (0U << 1U)
| (0U << 2U)
| (0U << 3U)
| (0U << 4U)
| (0U << 5U)
| (0U << 6U)
| (0U << 7U)
| (0U << 8U)
| (0U << 9U)
| (0U << 10U)
| (0U << 11U)
| (0U << 12U)
| (0U << 13U)
| (0U << 14U)
| (0U << 15U)
| (0U << 16U)
| (0U << 17U)
| (0U << 18U)
| (0U << 19U)
| (0U << 20U)
| (0U << 21U)
| (0U << 22U)
| (0U << 23U)
| (0U << 24U)
| (0U << 25U);
/* initalise copy table */
if ((uint32_t *)&__binit__ != (uint32_t *)0xFFFFFFFFU)
{
extern void copy_in(void *binit);
copy_in((void *)&__binit__);
}
/* initalise the C global variables */
if (&__TI_Handler_Table_Base < &__TI_Handler_Table_Limit)
{
uint8_t **tablePtr = (uint8_t **)&__TI_CINIT_Base;
uint8_t **tableLimit = (uint8_t **)&__TI_CINIT_Limit;
while (tablePtr < tableLimit)
{
uint8_t *loadAdr = *tablePtr++;
uint8_t *runAdr = *tablePtr++;
uint8_t idx = *loadAdr++;
handler_fptr handler = (handler_fptr)(&__TI_Handler_Table_Base)[idx];
(*handler)((const uint8_t *)loadAdr, runAdr);
}
}
/* initalise contructors */
if (__TI_PINIT_Base < __TI_PINIT_Limit)
{
void (**p0)() = (void *)__TI_PINIT_Base;
while ((uint32_t)p0 < __TI_PINIT_Limit)
{
void (*p)() = *p0++;
p();
}
}
/* USER CODE BEGIN (14) */
/* USER CODE END */
/* configure muxed pins */
muxInit();
/* call the application */
main();
exit();
}
void _c_int00(void)
{
/* NOTE: DO NOT INITIALIZE ANY VARIABLES !! (will cause DABORT because of un-initialized SP) */
volatile boolean retVal; /* For function return values */
SL_STC_Config stcSelfTestConfig; /* STC Configuration */
_coreInitRegisters_();
_coreInitStackPointer_();
resetReason = SL_Init_ResetReason();
if (RESET_TYPE_POWERON == resetReason)
{
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* Workaround for Errata CORTEXR4 66 */
_errata_CORTEXR4_66_();
/* Workaround for Errata CORTEXR4 57 */
_errata_CORTEXR4_57_();
}
else if (RESET_TYPE_OSC_FAILURE == resetReason)
{
/* Empty */
}
else if (RESET_TYPE_WATCHDOG == resetReason)
{
/* Reset caused due
* 1) windowed watchdog violation - Add user code here to handle watchdog violation.
* 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
*/
/* Check the WatchDog Status register */
if(WATCHDOG_STATUS != 0U)
{
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
}
}
else if ((RESET_TYPE_CPU == resetReason)&&((RESET_TYPE_DEBUG != resetReason)))
{
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* reset could be caused by stcSelfCheck run or by an actual CPU self-test run */
/* check if this was an stcSelfCheck run */
if ((stcREG->STCSCSCR & 0xFU) == 0xAU)
{
/* check if the self-test fail bit is set */
if ((stcREG->STCGSTAT & 0x3U) != 0x3U)
{
/* STC self-check has failed */
while(1);
}
/* STC self-check has passed */
else
{
/* clear self-check mode */
stcREG->STCSCSCR = 0x05U;
/* clear STC global status flags */
stcREG->STCGSTAT = 0x3U;
/* clear ESM group1 channel 27 status flag */
esmREG->SR1[0U] = 0x08000000U;
/* Start CPU Self-Test */
/*********************************************************************************************************/
/*cpuSelfTest(STC_INTERVAL, STC_MAX_TIMEOUT, TRUE);*/
stcSelfTestConfig.stcClockDiv = 0; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
_SL_HoldNClear_nError();
SL_SelfTest_STC(STC_RUN, TRUE, &stcSelfTestConfig);
/*********************************************************************************************************/
}
}
/* CPU reset caused by CPU self-test completion */
else if ((stcREG->STCGSTAT & 0x1U) == 0x1U)
{
/* Self-Test Fail flag is set */
if ((stcREG->STCGSTAT & 0x2U) == 0x2U)
{
/* Call CPU self-test failure handler */
while(1);
}
/* CPU self-test completed successfully */
else
{
/* clear STC global status flag */
stcREG->STCGSTAT = 0x1U;
/* Continue start-up sequence after CPU STC completed */
afterSTC();
}
}
/* CPU reset caused by software writing to CPU RESET bit */
else
{
/* Add custom routine here to handle the case where software causes CPU reset */
}
}
else if (RESET_TYPE_SWRST == resetReason)
{
/* Empty */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
}
/* Check if there were ESM group3 errors during power-up.
* These could occur during eFuse auto-load or during reads from flash OTP
* during power-up. Device operation is not reliable and not recommended
* in this case.
* An ESM group3 error only drives the nERROR pin low. An external circuit
* that monitors the nERROR pin must take the appropriate action to ensure that
* the system is placed in a safe state, as determined by the application.
*/
if ((esmREG->SR1[2]) != 0U)
{
//esmREG->SR1[2] = 0xFFFFFFFF;
for(;;)
{
}/* Wait */
}
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
if(RESET_TYPE_DEBUG != resetReason)
{
/* Make sure that the CPU self-test controller can actually detect a fault inside CPU */
stcSelfTestConfig.stcClockDiv = 0; /* STC Clock divider = 1 */
stcSelfTestConfig.intervalCount = 1; /* One interval only */
stcSelfTestConfig.restartInterval0 = TRUE; /* Start from interval 0 */
stcSelfTestConfig.timeoutCounter = 0xFFFFFFFF; /* Timeout counter*/
_SL_HoldNClear_nError();
SL_SelfTest_STC(STC_COMPARE_SELFCHECK, TRUE, &stcSelfTestConfig);
}else
{
afterSTC();
}
}